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    • 4. 发明申请
    • Functional Pillow for Preventing Head Deformation of Infants Due to Posture
    • 功能枕头防止由于姿势引起的婴儿头部变形
    • US20130305458A1
    • 2013-11-21
    • US13982998
    • 2011-06-08
    • Jin young Kim
    • Jin young Kim
    • A47G9/10
    • A47G9/10A61F5/05891A61G7/05715A61G13/121
    • The present invention relates to a functional pillow for preventing positional head deformity of an infant. The functional pillow includes an inner foam member which is porous, an outer cover which encloses the inner foam member and includes a plurality of through-holes formed thereon, a head seating portion which is formed on at least one of a top surface and a bottom surface of a pillow body which includes the inner foam member and the outer cover in an eccentric position to allow a head to be placed thereon, and at least one layered auxiliary pillow which is inserted into the head seating portion and includes an auxiliary head seating portion of a different size formed on a surface. A degree of layering of the auxiliary pillow is different according to a head size.
    • 本发明涉及一种用于防止婴儿的位置头畸形的功能性枕头。 所述功能性枕头包括多孔的内部泡沫构件,封闭所述内部泡沫构件并且包括形成在其上的多个通孔的外盖,头部座部,其形成在顶部表面和底部的至少一个上 枕头主体的表面,其包括内部泡沫构件和外盖,偏心位置以允许头部放置在其上;以及至少一个分层的辅助枕头,其插入到头部支座部分中,并且包括辅助头部支座部分 形成在表面上的不同尺寸。 辅助枕头的层次程度根据头部大小而不同。
    • 8. 发明授权
    • Semiconductor memory device having hierarchical bit line structure and method of driving the semiconductor memory device
    • 具有分级位线结构的半导体存储器件和驱动半导体存储器件的方法
    • US08331162B2
    • 2012-12-11
    • US12662222
    • 2010-04-06
    • Jin-young KimKi-whan Song
    • Jin-young KimKi-whan Song
    • G11C7/10
    • G11C7/18G11C7/12G11C11/4094G11C11/4097
    • The semiconductor memory device includes a first memory cell array including at least one first memory cell and at least one second memory cell corresponding to the at least one first memory cell, a first low bit line connected to the at least one first memory cell, a first low complementary bit line connected to the at least one second memory cell, a first switch unit having a first terminal connected to the first low bit line, a second switch unit having a first terminal connected to the first low complementary bit line, a first global bit line connected to a second terminal of the first switch unit, a first global complementary bit line connected to a second terminal of the second switch unit, and a plurality of sensing amplifying units connected to the first global bit line and the first global complementary bit line.
    • 半导体存储器件包括第一存储器单元阵列,其包括至少一个第一存储单元和与该至少一个第一存储单元对应的至少一个第二存储单元,连接至该至少一个第一存储单元的第一低位线, 连接到所述至少一个第二存储器单元的第一低互补位线,具有连接到所述第一低位线的第一端子的第一开关单元,具有连接到所述第一低互补位线的第一端子的第二开关单元, 连接到第一开关单元的第二端子的全局位线,连接到第二开关单元的第二端子的第一全局互补位线以及连接到第一全局位线和第一全局互补位置的多个感测放大单元 位线。
    • 9. 发明授权
    • Method and apparatus for setting a lip region for lip reading
    • 用于设置唇部读数的唇部区域的方法和装置
    • US08290277B2
    • 2012-10-16
    • US12646600
    • 2009-12-23
    • Seong-Taek HwangJin-Young Kim
    • Seong-Taek HwangJin-Young Kim
    • G06K9/46
    • G06K9/00248
    • A method for setting a lip region of a face included in an image, including setting a first region and a second region in an image including a face, identifying contrast information of the first region, setting a threshold for binarization using the contrast information, and binarizing the second region based on the threshold. A region in which a pixel having an identical binary value continuously distributed within a predetermined number of ranges in the binarized image is set as an eye candidate object. An eye region is then extracted from the eye candidate object based on geometric characteristic of an eye region in an image, and the lip region is set with reference to the extracted eye region based on geometric information of the eye region and the lip region.
    • 一种用于设置包括在图像中的脸部的唇部区域的方法,包括在包括脸部的图像中设置第一区域和第二区域,识别第一区域的对比度信息,使用对比度信息设置二值化阈值,以及 基于阈值二值化第二区域。 将其中在二值化图像中的预定数量范围内连续分布的相同二进制值的像素设置为候选对象的区域。 然后基于图像中的眼睛区域的几何特征,从眼睛候选物体中提取眼睛区域,并且基于眼睛区域和唇部区域的几何信息,参照提取的眼睛区域设定唇部区域。
    • 10. 发明授权
    • Semiconductor memory device comprising transistor having vertical channel structure
    • 半导体存储器件包括具有垂直沟道结构的晶体管
    • US08274810B2
    • 2012-09-25
    • US12955090
    • 2010-11-29
    • Duk-Ha ParkKi-Whan SongJin-Young Kim
    • Duk-Ha ParkKi-Whan SongJin-Young Kim
    • G11C5/02
    • H01L27/10876G11C7/1042G11C7/12G11C11/404G11C11/4094H01L29/78H01L29/7827
    • A semiconductor memory device including a transistor having a vertical channel structure is provided. The device includes a first sub memory cell array including a first memory cell connected to a first bit lines and including a transistor having a vertical channel structure, a second sub memory cell array including a second memory cell connected to a first inverted bit lines and including a transistor having a vertical channel structure, and a plurality of precharge blocks. In addition, first and second precharge blocks are disposed at first and second sides of the first bit line and precharge the first bit line, and third and fourth precharge blocks are disposed at first and second sides of the first inverted bit line and precharge the first inverted bit line.
    • 提供一种包括具有垂直沟道结构的晶体管的半导体存储器件。 该器件包括第一子存储单元阵列,该第一子存储单元阵列包括连接到第一位线并包括具有垂直沟道结构的晶体管的第一存储单元,第二子存储单元阵列,包括连接到第一反相位线的第二存储单元, 具有垂直沟道结构的晶体管和多个预充电块。 此外,第一和第二预充电块设置在第一位线的第一和第二侧并对第一位线进行预充电,并且第三和第四预充电块设置在第一反相位线的第一和第二侧,并且对第一 反转位线。