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1. 发明授权

US07668279B1 Signal processing system with low bandwidth phase-locked loop 有权
标题翻译：具有低带宽锁相环的信号处理系统
公开(公告)号：US07668279B1
公开(公告)日：2010-02-23
申请号：US11427910
申请日：2006-06-30
申请人： Zhong You , Hua Hong , Jeff Baumgartner , Jieren Bian
发明人： Zhong You , Hua Hong , Jeff Baumgartner , Jieren Bian
IPC分类号： H03D3/24
CPC分类号： H03L7/093
摘要： A signal processing system includes a phase-locked loop to provide an output signal used, for example, as a delta sigma modulator operating clock signal. In at least one embodiment, a frame clock that provides synchronization for one or more blocks of data is used by the phase-locked loop as a reference signal. Utilizing the frame clock as the reference signal allows the signal processing system to reduce the number of clock signals present in the signal processing system. In another embodiment, a phase-locked loop includes a loop filter that utilizes a sample and reset circuit, a feed forward integrator, and a feed forward stabilizer to provide a low frequency phase-locked loop bandwidth. In at least one embodiment, the feed forward integrator amplifies capacitance of the sample and reset circuit, which reduces the size of loop filter capacitors and, thus, allows on-chip capacitor integration.
摘要翻译：信号处理系统包括锁相环，以提供例如作为Δ-Σ调制器操作时钟信号使用的输出信号。在至少一个实施例中，为一个或多个数据块提供同步的帧时钟由锁相环用作参考信号。利用帧时钟作为参考信号，允许信号处理系统减少信号处理系统中存在的时钟信号的数量。在另一个实施例中，锁相环包括利用采样和复位电路的环路滤波器，前馈积分器和前馈稳定器，以提供低频锁相环带宽。在至少一个实施例中，前馈积分器放大样品和复位电路的电容，这减小了环路滤波电容器的尺寸，因此允许片上电容器集成。

2. 发明授权

US07711974B1 SCLK auto-detection and generation in various serial port modes 有权
标题翻译： SCLK自动检测和生成各种串口模式
公开(公告)号：US07711974B1
公开(公告)日：2010-05-04
申请号：US11540443
申请日：2006-09-29
申请人： Zhong You , Jieren Bian
发明人： Zhong You , Jieren Bian
IPC分类号： G06F1/00 , H03M1/66
CPC分类号： G06F1/04
摘要： An apparatus and a method for clock mode determination utilizing SCLK auto-detection and generation circuitry at a serial port which has a reduced number of pin-count by eliminating the need for inputting a master input clock signal MCLK and/or a serial input clock signal SCLK. The SCLK auto-detection and generation circuitry includes a SCLK detector circuit, a serial mode detector circuit, an internal SCLK generator circuit, a multiplexer, and an edge detector circuit. The SCLK detector circuit is used to detect whether an external serial clock signal is present and to generate a selection signal. The serial mode detector is used to detect whether an incoming data signal is in a non-TDM mode or a TDM mode and to generate a mode signal.
摘要翻译：一种在串行端口使用SCLK自动检测和产生电路的时钟模式确定的装置和方法，该串行端口通过不需要输入主输入时钟信号MCLK和/或串行输入时钟信号而减少引脚数量 SCLK。 SCLK自动检测和生成电路包括一个SCLK检测器电路，一个串行模式检测器电路，一个内部SCLK发生器电路，一个多路复用器和一个边沿检测电路。 SCLK检测器电路用于检测外部串行时钟信号是否存在并产生选择信号。串行模式检测器用于检测输入数据信号是处于非TDM模式还是TDM模式，并产生模式信号。

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