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1. 发明授权

US06570145B2 Phase grating image sensing device and method of manufacture 有权
公开(公告)号：US06570145B2
公开(公告)日：2003-05-27
申请号：US09847684
申请日：2001-05-02
申请人： Chin-Wen Huang , Jian-Bin Shiu , Ching-Ming Lee
发明人： Chin-Wen Huang , Jian-Bin Shiu , Ching-Ming Lee
IPC分类号： H01L2700
CPC分类号： H01L27/14685 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/1463 , H01L27/14643 , H01L27/14687
摘要： A phase grating image-sensing device. The device includes a plurality of photodiodes, a smoothing layer, a color filter layer and a plurality of phase gratings. The photodiodes are formed on a substrate and isolated from each other by isolation structures. The smoothing layer covers the photodiodes and the isolation structures. The color filter layer is embedded within the smoothing layer forming a sandwich structure with the smoothing layer. The phase gratings are formed over the smoothing layer positioned at corresponding locations above isolation structures. The phase grating layers produce a constructive interference of light passing through the smoothing layer.

2. 发明授权

US08193605B2 Bipolar junction transistor integrated with PIP capacitor and method for making the same 有权
标题翻译：与PIP电容集成的双极结晶体管及其制造方法
公开(公告)号：US08193605B2
公开(公告)日：2012-06-05
申请号：US12437550
申请日：2009-05-07
申请人： Jian-Bin Shiu
发明人： Jian-Bin Shiu
IPC分类号： H01L21/02
CPC分类号： H01L29/66242 , H01L27/0658 , H01L28/60 , H01L29/7375 , Y10S438/957
摘要： A bipolar junction transistor (BJT) integrated with a PIP capacitor includes a substrate including a bipolar junction transistor region and a PIP capacitor region, a bipolar junction transistor disposed in the bipolar junction transistor region and extending an isolation layer to the PIP capacitor region and a base poly layer disposed on the isolation layer, and a PIP capacitor disposed in the PIP capacitor region and including a lower poly layer, the isolation layer and the base poly layer to selectively form a PIP capacitor.
摘要翻译：与PIP电容器集成的双极结型晶体管（BJT）包括：包括双极结型晶体管区域和PIP电容器区域的衬底;设置在双极结型晶体管区域中并将隔离层延伸到PIP电容器区域的双极结型晶体管，以及设置在隔离层上的基极多层，以及设置在PIP电容器区域中的PIP电容器，其包括下部多层，隔离层和基底多层以选择性地形成PIP电容器。

3. 发明授权

US08092699B2 Method for forming phase grating 有权
标题翻译：形成相位光栅的方法
公开(公告)号：US08092699B2
公开(公告)日：2012-01-10
申请号：US12255642
申请日：2008-10-21
申请人： Jian-Bin Shiu
发明人： Jian-Bin Shiu
IPC分类号： B29D11/00
CPC分类号： G02B5/1871 , B29D11/00269 , G02B5/1857 , G02B2005/1804
摘要： A method for forming a phase grating is disclosed. First, a substrate is provided. Second, a first dielectric layer with a tapered recess or bulge is formed on the substrate. Later, a second dielectric layer is formed to fill the tapered recess and to cover the first dielectric layer. Afterwards, the second dielectric layer is selectively etched to form the phase grating. The phase grating includes a column and multiple rings. The column and multiple rings are concentric and the multiple rings are disposed on the tapered side so that the height of each ring is different.
摘要翻译：公开了一种形成相位光栅的方法。首先，提供基板。其次，在基板上形成具有锥形凹部或凸起的第一电介质层。之后，形成第二电介质层以填充锥形凹部并覆盖第一电介质层。之后，选择性地蚀刻第二介质层以形成相位光栅。相位光栅包括一列和多个环。柱和多个环是同心的，并且多个环设置在锥形侧上，使得每个环的高度不同。

4. 发明授权

US08792171B2 Phase grating with three-dimensional configuration 有权
公开(公告)号：US08792171B2
公开(公告)日：2014-07-29
申请号：US13310808
申请日：2011-12-05
申请人： Jian-Bin Shiu
发明人： Jian-Bin Shiu
IPC分类号： G02B5/18
CPC分类号： G02B5/1871 , B29D11/00269 , G02B5/1857 , G02B2005/1804
摘要： A phase grating includes a substrate and a first dielectric layer. The first dielectric layer is disposed on the substrate and includes a column and a plurality of rings. The top sides of the column and the top sides of the rings align with one another to form a flat plane. The column and the rings are concentric.

5. 发明申请

US20130270557A1 TEST STRUCTURE FOR SEMICONDUCTOR PROCESS AND METHOD FOR MONITORING SEMICONDUCTOR PROCESS 有权
标题翻译：用于半导体工艺的测试结构和用于监测半导体工艺的方法
公开(公告)号：US20130270557A1
公开(公告)日：2013-10-17
申请号：US13445934
申请日：2012-04-13
申请人： Jian-Bin Shiu , Tung-Sheng Lee
发明人： Jian-Bin Shiu , Tung-Sheng Lee
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/34
摘要： A monitoring method of a semiconductor process includes the following steps. A semiconductor substrate is provided, and a test structure is formed thereon. The method of forming the test structure includes the following steps. A first doped region and a second doped region are formed in the semiconductor substrate, and an insulating layer is formed on the semiconductor substrate. Subsequently, a conductive layer is directly formed on the insulating layer to complete the formation of the test structure, in which the conductive layer in a floating state partially overlaps the first doped region and partially overlaps the second doped region. Then, a voltage signal is applied to the test structure and the breakdown voltage (Vbd) between the first doped region and the second doped region is measured.
摘要翻译：半导体处理的监视方法包括以下步骤。提供半导体基板，并在其上形成测试结构。形成测试结构的方法包括以下步骤。在半导体衬底中形成第一掺杂区和第二掺杂区，并在半导体衬底上形成绝缘层。随后，在绝缘层上直接形成导电层，以完成测试结构的形成，其中浮置状态的导电层部分地与第一掺杂区域重叠并部分地与第二掺杂区域重叠。然后，将电压信号施加到测试结构，并且测量第一掺杂区域和第二掺杂区域之间的击穿电压（Vbd）。

6. 发明申请

US20100155908A1 PASSIVATION STRUCTURE AND FABRICATING METHOD THEREOF 有权
标题翻译：被动结构及其制作方法
公开(公告)号：US20100155908A1
公开(公告)日：2010-06-24
申请号：US12340766
申请日：2008-12-22
申请人： Jian-Bin Shiu
发明人： Jian-Bin Shiu
IPC分类号： H01L21/66 , H01L21/82 , H01L29/06
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A passivation structure and fabricating method thereof includes providing a chip having a main die region and a scribe line region defined thereon and a plurality of metal pads respectively positioned in the main die region and the scribe line region, forming a first patterned passivation layer having a plurality of first openings and second openings respectively exposing the metal pads in the main die region and the scribe line region on the chip, and forming a second patterned passivation layer filling the first openings in the scribe line region and having a plurality of third openings corresponding to the first openings thus exposing the metal pads in the main die region.
摘要翻译：钝化结构及其制造方法包括：提供具有主晶片区域和限定在其上的划线区域的芯片和分别位于主管芯区域和划线区域中的多个金属焊盘，形成第一图案化钝化层，其具有多个第一开口和第二开口分别暴露芯片上的主裸片区域中的金属焊盘和芯片上的划线区域，并形成填充划线区域中的第一开口的第二图案化钝化层，并且具有对应的多个第三开口到第一开口，从而使主模区域中的金属焊盘露出。

7. 发明授权

US06524772B1 Method of manufacturing phase grating image sensor 有权
标题翻译：制造相位光栅图像传感器的方法
公开(公告)号：US06524772B1
公开(公告)日：2003-02-25
申请号：US09943017
申请日：2001-08-30
申请人： Chin-Wen Huang , Jian-Bin Shiu
发明人： Chin-Wen Huang , Jian-Bin Shiu
IPC分类号： H01L2714
CPC分类号： H01L27/14627 , G02B5/1814 , G02B5/1885 , G02B5/201 , H01L27/14685
摘要： A method of manufacturing a phase grating image sensor is disclosed. The method uses conventional photolithography and etching methods to form a plurality of phase grating lenses into the conventional flattening layer on which the conventional micro-lens is formed. The invention thus utilizes phase gratings to replace the conventional micro-lens.
摘要翻译：公开了一种制造相位光栅图像传感器的方法。该方法使用常规的光刻和蚀刻方法将多个相位光栅透镜形成到其上形成常规微透镜的传统平坦化层中。因此，本发明利用相位光栅代替传统的微透镜。

8. 发明授权

US09070652B2 Test structure for semiconductor process and method for monitoring semiconductor process 有权
标题翻译：半导体工艺测试结构及半导体工艺监测方法
公开(公告)号：US09070652B2
公开(公告)日：2015-06-30
申请号：US13445934
申请日：2012-04-13
申请人： Jian-Bin Shiu , Tung-Sheng Lee
发明人： Jian-Bin Shiu , Tung-Sheng Lee
IPC分类号： H01L21/66
CPC分类号： H01L22/34
摘要： A monitoring method of a semiconductor process includes the following steps. A semiconductor substrate is provided, and a test structure is formed thereon. The method of forming the test structure includes the following steps. A first doped region and a second doped region are formed in the semiconductor substrate, and an insulating layer is formed on the semiconductor substrate. Subsequently, a conductive layer is directly formed on the insulating layer to complete the formation of the test structure, in which the conductive layer in a floating state partially overlaps the first doped region and partially overlaps the second doped region. Then, a voltage signal is applied to the test structure and the breakdown voltage (Vbd) between the first doped region and the second doped region is measured.
摘要翻译：半导体处理的监视方法包括以下步骤。提供半导体基板，并在其上形成测试结构。形成测试结构的方法包括以下步骤。在半导体衬底中形成第一掺杂区和第二掺杂区，并在半导体衬底上形成绝缘层。随后，在绝缘层上直接形成导电层，以完成测试结构的形成，其中浮置状态的导电层部分地与第一掺杂区域重叠并部分地与第二掺杂区域重叠。然后，将电压信号施加到测试结构，并且测量第一掺杂区域和第二掺杂区域之间的击穿电压（Vbd）。

9. 发明申请

US20120075702A1 PHASE GRATING 有权
标题翻译：相位磨砂
公开(公告)号：US20120075702A1
公开(公告)日：2012-03-29
申请号：US13310808
申请日：2011-12-05
申请人： Jian-Bin Shiu
发明人： Jian-Bin Shiu
IPC分类号： G02B5/18
CPC分类号： G02B5/1871 , B29D11/00269 , G02B5/1857 , G02B2005/1804
摘要： A phase grating includes a substrate and a first dielectric layer. The first dielectric layer is disposed on the substrate and includes a column and a plurality of rings. The top sides of the column and the top sides of the rings align with one another to form a flat plane. The column and the rings are concentric.
摘要翻译：相位光栅包括基板和第一介电层。第一电介质层设置在基板上，并且包括列和多个环。柱的顶侧和环的顶侧彼此对准以形成平面。柱和环是同心的。

10. 发明申请

US20100283123A1 BIPOLAR JUNCTION TRANSISTOR INTEGRATED WITH PIP CAPACITOR AND METHOD FOR MAKING THE SAME 有权
标题翻译：与PIP电容器集成的双极晶体管及其制造方法
公开(公告)号：US20100283123A1
公开(公告)日：2010-11-11
申请号：US12437550
申请日：2009-05-07
申请人： Jian-Bin Shiu
发明人： Jian-Bin Shiu
IPC分类号： H01L29/73 , H01L21/02
CPC分类号： H01L29/66242 , H01L27/0658 , H01L28/60 , H01L29/7375 , Y10S438/957
摘要： A bipolar junction transistor (BJT) integrated with a PIP capacitor includes a substrate including a bipolarjunction transistor region and a PIP capacitor region, a bipolar junction transistor disposed in the bipolar junction transistor region and extending an isolation layer to the PIP capacitor region and a base poly layer disposed on the isolation layer, and a PIP capacitor disposed in the PIP capacitor region and including a lower poly layer, the isolation layer and the base poly layer to selectively form a PIP capacitor.
摘要翻译：与PIP电容器集成的双极结型晶体管（BJT）包括：包括双极结型晶体管区域和PIP电容器区域的衬底;设置在双极结型晶体管区域中并将隔离层延伸到PIP电容器区域的基极;以及基极设置在隔离层上的多晶硅层和设置在PIP电容器区域中的PIP电容器，并且包括下多晶硅层，隔离层和基极多晶硅层以选择性地形成PIP电容器。

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