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1. 发明申请

US20100270605A1 NONVOLATILE MEMORY CELL AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：非易失性存储器单元及其制造方法
公开(公告)号：US20100270605A1
公开(公告)日：2010-10-28
申请号：US12604757
申请日：2009-10-23
申请人： Tae-Ho CHOI , Jung-Hwan Lee , Heung-Gee Hong , Jeong-Ho Cho , Min-Wan Choo , Il-Seok Han
发明人： Tae-Ho CHOI , Jung-Hwan Lee , Heung-Gee Hong , Jeong-Ho Cho , Min-Wan Choo , Il-Seok Han
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/512 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a floating gate formed over the substrate between the drain region and the source region, a halo region formed in the substrate in a direction that the drain region is formed, a dielectric layer formed on sidewalls of the floating gate, and a control gate formed over the dielectric layer to overlap with at least one sidewall of the floating gate.
摘要翻译：非易失性存储单元及其制造方法可以确保稳定的操作可靠性以及减小单元尺寸。非易失性存储单元包括形成在衬底中的漏极区，形成在衬底中的与漏极区分离的源极区，在漏极区和源极区之间形成在衬底上的浮置栅，在形成漏极区域的方向上形成衬底，形成在浮置栅极的侧壁上的电介质层以及形成在电介质层上以与浮动栅极的至少一个侧壁重叠的控制栅极。

2. 发明授权

US07817846B2 Method of correcting bonding coordinates using reference bond pads 有权
标题翻译：使用参考焊盘校正键合坐标的方法
公开(公告)号：US07817846B2
公开(公告)日：2010-10-19
申请号：US11485488
申请日：2006-07-12
申请人： Yong-bok Chung , Jeong-ho Cho
发明人： Yong-bok Chung , Jeong-ho Cho
IPC分类号： G06K9/00
CPC分类号： B23K20/004 , H01L21/67259 , H01L24/06 , H01L24/78 , H01L24/85 , H01L2223/5442 , H01L2224/05554 , H01L2224/05599 , H01L2224/78 , H01L2224/85121 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01082 , Y10S228/904 , H01L2224/45099 , H01L2224/48
摘要： A method of correcting bonding coordinates according to locations of a die and leads loaded for bonding is provided. The method includes searching for locations of die recognition areas and lead recognition areas, comparing the detected locations of the recognition areas, and correcting bonding coordinates of the die and the leads according to the result obtained by the comparison; and if a search for the locations of the die recognition areas fails, searching for reference bond pads, comparing locations of the detected reference bond pads with setting locations, and correcting bonding coordinates of a die and leads to be bonded according to the result obtained by the comparison.
摘要翻译：提供根据管芯的位置校正接合坐标的方法和用于接合的引线。该方法包括搜索芯片识别区域和引线识别区域的位置，比较检测到的识别区域的位置，以及根据比较获得的结果来校正模具和引线的键合坐标; 并且如果对芯片识别区域的位置的搜索失败，则搜索参考焊盘，将检测到的参考焊盘的位置与设置位置进行比较，以及校正模具的粘合坐标并根据由比较。

3. 发明授权

US09281202B2 Nonvolatile memory cell and method for fabricating the same 有权
标题翻译：非易失性存储单元及其制造方法
公开(公告)号：US09281202B2
公开(公告)日：2016-03-08
申请号：US12604757
申请日：2009-10-23
申请人： Tae-Ho Choi , Jung-Hwan Lee , Heung-Gee Hong , Jeong-Ho Cho , Min-Wan Choo , Il-Seok Han
发明人： Tae-Ho Choi , Jung-Hwan Lee , Heung-Gee Hong , Jeong-Ho Cho , Min-Wan Choo , Il-Seok Han
IPC分类号： H01L29/423 , H01L21/28 , H01L29/51 , H01L29/66 , H01L29/788
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/512 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a floating gate formed over the substrate between the drain region and the source region, a halo region formed in the substrate in a direction that the drain region is formed, a dielectric layer formed on sidewalls of the floating gate, and a control gate formed over the dielectric layer to overlap with at least one sidewall of the floating gate.
摘要翻译：非易失性存储单元及其制造方法可以确保稳定的操作可靠性以及减小单元尺寸。非易失性存储单元包括形成在衬底中的漏极区，形成在衬底中的与漏极区分离的源极区，在漏极区和源极区之间形成在衬底上的浮置栅，在形成漏极区域的方向上形成衬底，形成在浮置栅极的侧壁上的电介质层以及形成在电介质层上以与浮动栅极的至少一个侧壁重叠的控制栅极。

4. 发明授权

US06259189B1 High frequency resonator, and manufacturing method therefor 失效
标题翻译：高频谐振器及其制造方法
公开(公告)号：US06259189B1
公开(公告)日：2001-07-10
申请号：US09337279
申请日：1999-06-22
申请人： Nak Cheol Sung , Min Soo Kim , Jeong Ho Cho
发明人： Nak Cheol Sung , Min Soo Kim , Jeong Ho Cho
IPC分类号： H01L4108
CPC分类号： H03H9/562 , H03H3/02 , Y10T29/42 , Y10T29/43 , Y10T29/435 , Y10T29/49121 , Y10T29/49146 , Y10T29/49169 , Y10T29/49171 , Y10T29/49789 , Y10T29/49798
摘要： A high frequency resonator and a manufacturing method therefor are disclosed. The method for manufacturing a ceramic resonator includes the step of forming a ceramic piezoelectric device, a capacitor chip and a lead frame. Then the piezoelectric device and the capacitor chip are assembled into the lead frame, and the assembled chip is molded by using epoxy resin. The process for making the capacitor includes the step of cutting a ceramic wafer into a plurality of sub-wafers. Then electrodes are printed on one face of the sub-wafer in a dual-striped form, and a drying is carried out on the sub-wafer thus printed. Then another electrode is printed on a central part of the opposite face of the sub-wafer in such a manner as to be overlapped with the electrodes of the one face of the sub-wafer. Then the sub-wafer is dried. Then a baking is carried out on the sub-wafer thus dried, and the sub-wafer thus baked is cut into a plurality of capacitor chips.
摘要翻译：公开了一种高频谐振器及其制造方法。制造陶瓷谐振器的方法包括形成陶瓷压电器件，电容器芯片和引线框架的步骤。然后将压电器件和电容器芯片组装到引线框架中，并且使用环氧树脂模制组装的芯片。制造电容器的过程包括将陶瓷晶片切割成多个子晶片的步骤。然后将电极以双重条纹形式印刷在子晶片的一个面上，并且在这样印刷的子晶片上进行干燥。然后以与子晶片的一个面的电极重叠的方式将另一电极印刷在子晶片的相对面的中心部分上。然后将该副晶片干燥。然后在这样干燥的子晶片上进行烘烤，将这样烘烤的子晶片切成多个电容器芯片。

5. 发明申请

US20120157015A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CONTROL SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：半导体器件和半导体控制系统，包括它们
公开(公告)号：US20120157015A1
公开(公告)日：2012-06-21
申请号：US13048283
申请日：2011-03-15
申请人： Jun-Gi CHOI , Jeong-Ho CHO , Hyung-Jun CHO
发明人： Jun-Gi CHOI , Jeong-Ho CHO , Hyung-Jun CHO
IPC分类号： H04B1/38 , H01Q1/38
CPC分类号： H04B1/40 , H01Q7/00 , H01Q23/00
摘要： A semiconductor device includes an interface pad, and an antenna formed to surround the interface pad. The semiconductor device may further include a buffer configured to receive a first input signal applied to the interface pad, a driver configured to output a first output signal to the interface pad a receiver configured to receive a second input signal transferred to the antenna, and a transmitter configured to output a second output signal to the antenna.
摘要翻译：半导体器件包括接口焊盘和形成为围绕接口焊盘的天线。半导体器件还可以包括缓冲器，其被配置为接收施加到接口焊盘的第一输入信号;驱动器，被配置为向接口焊盘输出第一输出信号，接收器被配置为接收传送到天线的第二输入信号，以及发射机被配置为向天线输出第二输出信号。

6. 发明申请

US20120127813A1 DEVICE AND METHOD FOR STORING ERROR INFORMATION OF MEMORY 有权
标题翻译：存储存储器错误信息的设备和方法
公开(公告)号：US20120127813A1
公开(公告)日：2012-05-24
申请号：US12982705
申请日：2010-12-30
申请人： Woo-Sik JEONG , Kang-Chil Lee , Jeong-Ho Cho , Kyoung-Shub Lee , Il-Kwon Kang , Sungho Kang , Joo Hwan Lee
发明人： Woo-Sik JEONG , Kang-Chil Lee , Jeong-Ho Cho , Kyoung-Shub Lee , Il-Kwon Kang , Sungho Kang , Joo Hwan Lee
IPC分类号： G11C29/04
CPC分类号： G11C29/44 , G11C29/808 , G11C2029/4402
摘要： A device for storing error information of a memory device includes a plurality of parent memories and a plurality of child memories. Each of the parent memories stores a row address and a column address of one defective cell. Each of the child memories stores a column address of a defective cell, having a row address identical to a row address stored in the corresponding parent memory, or a row address of a defective cell, having a column address identical to a column address stored in the corresponding parent memory. Herein, each of the parent memories stores information about information about whether a row repair must be performed to repair a defective cell stored in the parent memory and information about whether a column repair must be performed to repair a defective cell stored in the parent memory.
摘要翻译：用于存储存储器件的错误信息的装置包括多个母存储器和多个子存储器。每个父存储器存储一个缺陷单元的行地址和列地址。每个子存储器存储有缺陷单元的列地址，具有与存储在相应的父存储器中的行地址相同的行地址，或具有与存储在其中的列地址相同的列地址的有缺陷单元的行地址相应的父内存。这里，每个父存储器存储关于是否必须执行行修复以修复存储在父存储器中的缺陷单元的信息的信息，以及关于是否必须执行列修复以修复存储在父存储器中的缺陷单元的信息。

7. 发明申请

US20070230771A1 Method of correcting bonding coordinates using reference bond pads 有权
标题翻译：使用参考焊盘校正键合坐标的方法
公开(公告)号：US20070230771A1
公开(公告)日：2007-10-04
申请号：US11485488
申请日：2006-07-12
申请人： Yong-bok Chung , Jeong-ho Cho
发明人： Yong-bok Chung , Jeong-ho Cho
IPC分类号： G06K9/00
CPC分类号： B23K20/004 , H01L21/67259 , H01L24/06 , H01L24/78 , H01L24/85 , H01L2223/5442 , H01L2224/05554 , H01L2224/05599 , H01L2224/78 , H01L2224/85121 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01082 , Y10S228/904 , H01L2224/45099 , H01L2224/48
摘要： A method of correcting bonding coordinates according to locations of a die and leads loaded for bonding is provided. The method includes searching for locations of die recognition areas and lead recognition areas, comparing the detected locations of the recognition areas, and correcting bonding coordinates of the die and the leads according to the result obtained by the comparison; and if a search for the locations of the die recognition areas fails, searching for reference bond pads, comparing locations of the detected reference bond pads with setting locations, and correcting bonding coordinates of a die and leads to be bonded according to the result obtained by the comparison.
摘要翻译：提供根据管芯的位置校正接合坐标的方法和用于接合的引线。该方法包括搜索芯片识别区域和引线识别区域的位置，比较检测到的识别区域的位置，以及根据比较获得的结果来校正模具和引线的键合坐标; 并且如果对芯片识别区域的位置的搜索失败，则搜索参考焊盘，将检测到的参考焊盘的位置与设置位置进行比较，以及校正模具的粘合坐标并根据由比较。

8. 发明授权

US08601330B2 Device and method for repair analysis 有权
标题翻译：装置和方法进行修复分析
公开(公告)号：US08601330B2
公开(公告)日：2013-12-03
申请号：US12982809
申请日：2010-12-30
申请人： Woo-Sik Jeong , Kang-Chil Lee , Jeong-Ho Cho , Kyoung-Shub Lee , Il-Kwon Kang , Sungho Kang , Joo Hwan Lee
发明人： Woo-Sik Jeong , Kang-Chil Lee , Jeong-Ho Cho , Kyoung-Shub Lee , Il-Kwon Kang , Sungho Kang , Joo Hwan Lee
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/72 , G11C29/808 , G11C2029/1208
摘要： A device for repair analysis includes a selection unit and an analysis unit. The selection unit is configured to select a part of the row addresses of a plurality of spare pivot fault cells and a part of the column addresses of the spare pivot fault cells in response to a control code. The analysis unit is configured to generate an analysis signal indicating whether row addresses of a plurality of non-spare pivot fault cells are included in selected row addresses and column addresses of the non-spare pivot fault cells are included in selected column addresses.
摘要翻译：用于修复分析的装置包括选择单元和分析单元。选择单元被配置为响应于控制代码来选择多个备用枢轴故障单元的行地址的一部分以及备用枢轴故障单元的列地址的一部分。分析单元被配置为生成指示多个非备用枢纽故障小区的行地址是否包括在所选行地址中的分析信号，并且非备用枢纽故障小区的列地址被包括在所选列地址中。

9. 发明授权

US08432758B2 Device and method for storing error information of memory 有权
标题翻译：用于存储内存错误信息的设备和方法
公开(公告)号：US08432758B2
公开(公告)日：2013-04-30
申请号：US12982705
申请日：2010-12-30
申请人： Woo-Sik Jeong , Kang-Chil Lee , Jeong-Ho Cho , Kyoung-Shub Lee , Il-Kwon Kang , Sungho Kang , Joo Hwan Lee
发明人： Woo-Sik Jeong , Kang-Chil Lee , Jeong-Ho Cho , Kyoung-Shub Lee , Il-Kwon Kang , Sungho Kang , Joo Hwan Lee
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/808 , G11C2029/4402
摘要： A device for storing error information of a memory device includes a plurality of parent memories and a plurality of child memories. Each of the parent memories stores a row address and a column address of one defective cell. Each of the child memories stores a column address of a defective cell, having a row address identical to a row address stored in the corresponding parent memory, or a row address of a defective cell, having a column address identical to a column address stored in the corresponding parent memory. Herein, each of the parent memories stores information about information about whether a row repair must be performed to repair a defective cell stored in the parent memory and information about whether a column repair must be performed to repair a defective cell stored in the parent memory.
摘要翻译：用于存储存储器件的错误信息的装置包括多个母存储器和多个子存储器。每个父存储器存储一个缺陷单元的行地址和列地址。每个子存储器存储有缺陷单元的列地址，具有与存储在相应的父存储器中的行地址相同的行地址，或具有与存储在其中的列地址相同的列地址的有缺陷单元的行地址相应的父内存。这里，每个父存储器存储关于是否必须执行行修复以修复存储在父存储器中的缺陷单元的信息的信息，以及关于是否必须执行列修复以修复存储在父存储器中的缺陷单元的信息。

10. 发明申请

US20130099301A1 NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THEREOF 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20130099301A1
公开(公告)日：2013-04-25
申请号：US13469238
申请日：2012-05-11
申请人： Jeong-ho Cho , Jung-goo Park , Min-wan Chu , Doo-yeol Ryu
发明人： Jeong-ho Cho , Jung-goo Park , Min-wan Chu , Doo-yeol Ryu
IPC分类号： H01L29/788 , H01L21/283
CPC分类号： H01L29/42324 , H01L21/2815 , H01L21/28273 , H01L27/11521 , H01L29/6659 , H01L29/7834 , H01L29/7881
摘要： A nonvolatile memory device and a method of manufacturing thereof are provided. The method includes forming a floating gate on a substrate, forming a dielectric layer to conform to a shape of the floating gate, forming a conductive layer to form a control gate on the substrate, the control gate covering the floating gate and the dielectric layer, forming a photoresist pattern on one side of the conductive layer, forming the control gate in the form of a spacer to surround sides of the floating gate, the forming of the control gate including performing an etch-back on the conductive layer until a portion of the dielectric layer on the floating gate is exposed, and forming a poly pad, to which a plurality of contact plugs are connected, on one side of the control gate, the forming of the poly pad including removing the photoresist pattern.
摘要翻译：提供一种非易失性存储器件及其制造方法。该方法包括在衬底上形成浮栅，形成符合浮栅的形状的电介质层，形成导电层以在衬底上形成控制栅极，覆盖浮栅和电介质层的控制栅极，在所述导电层的一侧上形成光致抗蚀剂图案，形成间隔物形式的控制栅极以围绕所述浮置栅极的侧面，所述控制栅极的形成包括在所述导电层上执行回蚀刻，直到一部分露出浮置栅极上的电介质层，并在控制栅极的一侧上形成多个接触插塞连接的多晶硅焊盘，形成多晶硅焊盘，包括去除光致抗蚀剂图案。

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