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    • 5. 发明授权
    • Liquid crystal display device having data lines and gate lines whose widths stepwisely increase
    • 具有数据线和宽度逐步增加的栅极线的液晶显示装置
    • US07773181B2
    • 2010-08-10
    • US11311411
    • 2005-12-20
    • Jeong Hoon KoWoon Sub Choi
    • Jeong Hoon KoWoon Sub Choi
    • G02F1/1343G02F1/1345
    • G02F1/136286
    • A liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel which has a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of liquid crystal cells that are defined by the data lines and the gate lines; a first data driver disposed at an upper side of the liquid crystal display panel to supply data to odd-numbered data lines; a second data driver disposed at a lower side of the liquid crystal display panel to supply data to even-numbered data lines; a first gate driver disposed at a left side of the liquid crystal display panel to supply a scan pulse to odd-numbered gate lines; and a second gate driver disposed at a right side of the liquid crystal display panel to supply a scan pulse to even-numbered gate lines, and wherein at least any one of the data lines and the gate lines has a line width that varies along its length.
    • 根据本发明实施例的液晶显示装置包括具有多条数据线的液晶显示面板,与数据线交叉的多条栅极线以及由该数据定义的多个液晶单元 线和门线; 设置在液晶显示面板的上侧的第一数据驱动器,用于向奇数数据线提供数据; 设置在液晶显示面板的下侧的第二数据驱动器,用于向偶数数据线提供数据; 设置在液晶显示面板左侧的第一栅极驱动器,用于向奇数栅极线提供扫描脉冲; 以及设置在所述液晶显示面板的右侧的第二栅极驱动器,用于向偶数栅极线提供扫描脉冲,并且其中所述数据线和所述栅极线中的至少一个具有沿其变化的线宽 长度。
    • 7. 发明申请
    • Liquid crystal display device
    • 液晶显示装置
    • US20060290630A1
    • 2006-12-28
    • US11315122
    • 2005-12-23
    • Do-Yeon KimJeong-Hoon Ko
    • Do-Yeon KimJeong-Hoon Ko
    • G09G3/36
    • H01L27/1296G09G3/3648G09G2320/0223G09G2320/0247H01L27/124
    • A liquid crystal display device includes a first pixel and a second pixel. The first pixel includes a first thin film transistor having a first channel W/L (width/length) ratio and a first gate-drain parasitic capacitance. The second pixel includes a second thin film transistor that is disposed at a different relative position than the first thin film transistor. The second thin film transistor has a second channel W/L (width/length) ratio and a second gate-drain parasitic capacitance. The first and second channel W/L ratios are substantially the same, and the first and second gate-drain parasitic capacitances are different from each other such that the first and second pixels have substantially the same common voltages.
    • 液晶显示装置包括第一像素和第二像素。 第一像素包括具有第一沟道W / L(宽/长)比率和第一栅 - 漏寄生电容的第一薄膜晶体管。 第二像素包括设置在与第一薄膜晶体管不同的相对位置的第二薄膜晶体管。 第二薄膜晶体管具有第二通道W / L(宽度/长度)比和第二栅极 - 漏极寄生电容。 第一和第二通道W / L比基本上相同,并且第一和第二栅 - 漏寄生电容彼此不同,使得第一和第二像素具有基本上相同的公共电压。
    • 10. 发明授权
    • Clock signal generating apparatus for data communication channel
    • 用于数据通信信道的时钟信号发生装置
    • US06356566B1
    • 2002-03-12
    • US09111235
    • 1998-07-07
    • Tae Hee LeeJong Ho KimJeong Hoon KoYoo Kyoung Lee
    • Tae Hee LeeJong Ho KimJeong Hoon KoYoo Kyoung Lee
    • H04J306
    • H04J3/0685H04J3/047H04J2203/0089
    • A clock signal generating apparatus for a data communication channel is disclosed which includes a first clock signal generating unit for receiving an external input clock signal and a frame position informing signal and outputting a predetermined cycle first clock signal and a first timing signal, a second clock signal generating unit for receiving the first clock signal and the first timing signal and externally outputting a first offset signal, a second timing signal, and a predetermined cycle second clock signal, respectively, and a third clock signal generating unit for receiving the first clock signal and the first timing signal and externally outputting a second offset signal, a third timing signal and a predetermined cycle third clock signal, respectively, for thereby implementing a reliable serial/parallel conversion, extraction and insertion of a data by generating a stable clock and timing signal using a simple circuit and supplying a stable clock signal for matching with an external apparatus for thereby achieving a reliable data communication for a system.
    • 公开了一种用于数据通信信道的时钟信号产生装置,包括:第一时钟信号产生单元,用于接收外部输入时钟信号和帧位置通知信号,并输出预定周期的第一时钟信号和第一定时信号;第二时钟 信号发生单元,用于分别接收第一时钟信号和第一定时信号,并分别外部输出第一偏移信号,第二定时信号和预定的周期第二时钟信号;第三时钟信号产生单元,用于接收第一时钟信号 和第一定时信号,并且分别从外部输出第二偏移信号,第三定时信号和预定的周期第三时钟信号,从而通过产生稳定的时钟和定时来实现可靠的串行/并行转换,数据的提取和插入 信号使用简单的电路并提供稳定的时钟信号以匹配 从而实现系统的可靠数据通信。