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1. 发明授权

US06633029B2 Video bus for high speed multi-resolution imagers and method thereof 有权
标题翻译：用于高速多分辨率成像器的视频总线及其方法
公开(公告)号：US06633029B2
公开(公告)日：2003-10-14
申请号：US09768124
申请日：2001-01-23
申请人： Jeffrey Zarnowski , Matthew Pace , Thomas Vogelsong , Michael Joyner
发明人： Jeffrey Zarnowski , Matthew Pace , Thomas Vogelsong , Michael Joyner
IPC分类号： H01J4014
CPC分类号： H04N5/378 , H04N5/365 , H04N5/3742 , H04N5/37457
摘要： A bus system and an imager for transferring signals from a plurality of signal streams to an output includes a plurality of signal buses in parallel and a control system. The control system multiplexes the signals from two or more of the plurality of signal streams onto two or more of the plurality of signal buses and allows the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to the output. A method for transferring signals includes multiplexing signals on to two or more of a plurality of signal buses and allowing the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to an output.
摘要翻译：用于将信号从多个信号流传送到输出的总线系统和成像器包括并行的多个信号总线和控制系统。所述控制系统将来自所述多个信号流中的两个或多个的信号复用到所述多个信号总线中的两个或更多个信号总线上，并且允许所述信号在将所述信号解复用之前对所述多个信号总线中的所述两个或更多个信号进行充电，输出。用于传送信号的方法包括将信号复用到多个信号总线中的两个或更多个信号总线上，并且在将信号解复用到输出之前允许信号基本上对多个信号总线中的两个或更多个信号进行充电。

2. 发明申请

US20050185079A1 Scanning imager employing multiple chips with staggered pixels 有权
标题翻译：扫描成像仪采用具有交错像素的多个芯片
公开(公告)号：US20050185079A1
公开(公告)日：2005-08-25
申请号：US11111334
申请日：2005-04-21
申请人： Jeffrey Zarnowski , Ketan Karia , Michael Joyner , Thomas Poonnen
发明人： Jeffrey Zarnowski , Ketan Karia , Michael Joyner , Thomas Poonnen
IPC分类号： H01L27/146 , H04N1/03 , H04N5/374 , H04N5/378 , H04N9/04 , H01L31/062 , H01L29/732 , H04N3/14
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14621 , H01L27/14625 , H01L27/14643 , H01L27/14645 , H04N1/03 , H04N1/0308 , H04N1/1933 , H04N1/1934 , H04N5/3692
摘要： A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangment minimizes color cross talk.
摘要翻译：固态成像系统具有至少一个具有第一和第二系列像素的CMOS成像器，其中一系列的像素相对于另一系列的像素偏移，即交错。多个成像器可以端对端排列，跨接线连接像素输出导体或每个像素，以便像素馈送到每个系列的公共输出放大器，以最小化芯片到芯片的偏移电压。像素可以彼此对角地偏移，并且可以构造彩色成像器，其中色带滤光器对角地布置在成像区域上。这种布置使颜色串扰最小化。

3. 发明申请

US20060157644A1 Scanning imager employing multiple chips with staggered pixels 有权
公开(公告)号：US20060157644A1
公开(公告)日：2006-07-20
申请号：US11356199
申请日：2006-02-17
申请人： Jeffrey Zarnowski , Ketan Karia , Michael Joyner , Thomas Poonnen
发明人： Jeffrey Zarnowski , Ketan Karia , Michael Joyner , Thomas Poonnen
IPC分类号： H01L27/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14621 , H01L27/14625 , H01L27/14643 , H01L27/14645 , H04N1/03 , H04N1/0308 , H04N1/1933 , H04N1/1934 , H04N5/3692
摘要： A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangment minimizes color cross talk.

4. 发明授权

US06911639B2 CMOS system for capturing an image and a method thereof 有权
标题翻译：用于捕获图像的CMOS系统及其方法
公开(公告)号：US06911639B2
公开(公告)日：2005-06-28
申请号：US10141008
申请日：2002-05-07
申请人： Christian Boemler , Jeffrey Zarnowski
发明人： Christian Boemler , Jeffrey Zarnowski
IPC分类号： H01L27/146 , H04N1/03 , H04N5/347 , H04N5/353 , H04N5/374 , H04N9/07 , H01J40/14 , H01L27/00
CPC分类号： H04N1/0308 , H01L27/14603 , H01L27/14643 , H04N1/03 , H04N1/1933 , H04N5/3415
摘要： A system for capturing an image includes a CMOS imaging system, an image focusing device, and an image control processing system coupled to the CMOS imaging system. The CMOS imaging system has at least one CMOS imager with at least one series of pixels. The image focusing device directs the image on to at least a portion of the at least one series of pixels. The CMOS imager may have two or more series of pixels at least adjacent each other where each of the series of pixels is offset from another one of the series of the pixels by a reciprocal of the total number of series of pixels in the CMOS imager.
摘要翻译：用于捕获图像的系统包括CMOS成像系统，图像聚焦装置和耦合到CMOS成像系统的图像控制处理系统。 CMOS成像系统具有至少一个具有至少一系列像素的CMOS成像器。图像聚焦装置将图像引导到至少一系列像素的至少一部分。 CMOS成像器可以具有至少彼此相邻的两个或更多个像素系列，其中每个像素系列通过CMOS成像器中的像素序列的总数的倒数与该系列像素中的另一个偏移。

5. 发明申请

US20080043128A1 Image sensor ADC and CDS per Column with Oversampling 有权
标题翻译：图像传感器ADC和CDS每列过采样
公开(公告)号：US20080043128A1
公开(公告)日：2008-02-21
申请号：US11974813
申请日：2007-10-16
申请人： Thomas Poonnen , Jeffrey Zarnowski , Li Liu , Michael Joyner , Ketan Karia
发明人： Thomas Poonnen , Jeffrey Zarnowski , Li Liu , Michael Joyner , Ketan Karia
IPC分类号： H04N5/335
CPC分类号： H03M1/123 , H03M1/1019 , H03M1/1235 , H03M1/56 , H04N5/335 , H04N5/3575 , H04N5/3742 , H04N5/37455 , H04N5/3765 , H04N5/378
摘要： A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. An N-bit counter supplies an N-bit DAC to produce an analog ramp output with a level that varies corresponding to the contents of the counter. A latch/counter or equivalent is associated with each respective column. A clock supplies clock signal(s) to the counter elements. When the analog ramp equals the pixel value for that column, the latch/counter latches the value. The black level can be pre-set in the latch/counter or can be subtracted separately to reduce fixed pattern noise. The pixels can be oversampled for some number of times, e.g., n=16, to reduce the thermal noise of the sensors. Also, two or more pixels sharing a common sense node may be binned together, and two (or more) pixels having different integration times may be combined to obtain an output signal with enhanced dynamic range.
摘要翻译：固态成像器将阵列每列的模拟像素值转换为数字形式。 N位计数器提供N位DAC以产生具有与计数器内容相对应的电平的模拟斜坡输出。锁存/计数器或等效物与每个相应的列相关联。时钟向计数器元件提供时钟信号。当模拟斜坡等于该列的像素值时，锁存器/计数器锁存该值。黑色电平可以在锁存/计数器中预先设置，也可以单独减去，以减少固定模式噪声。像素可以被过采样若干次，例如n = 16，以减少传感器的热噪声。此外，共享共同感测节点的两个或更多个像素可以被合并在一起，并且可以组合具有不同积分时间的两个（或更多个）像素以获得具有增强的动态范围的输出信号。

6. 发明申请

US20070040100A1 Scanning imager employing multiple chips with staggered pixels 有权
标题翻译：扫描成像仪采用具有交错像素的多个芯片
公开(公告)号：US20070040100A1
公开(公告)日：2007-02-22
申请号：US11589357
申请日：2006-10-30
申请人： Jeffrey Zarnowski , Ketan Karia , Michael Joyner , Thomas Poonnen , Li Liu
发明人： Jeffrey Zarnowski , Ketan Karia , Michael Joyner , Thomas Poonnen , Li Liu
IPC分类号： H01L27/00
CPC分类号： H04N5/2254 , H01L27/14603 , H01L27/14621 , H01L27/14627 , H04N1/1911 , H04N1/1917 , H04N5/3692 , H04N9/045 , H04N2201/0081
摘要： A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk. An array of microlenses is situated with each microlens covering a plurality of the pixels. The different pixels under each microlens can be aligned along a diagonal. The different pixels under the same microlens can have different integration times, to increase the dynamic range of the imager(s).
摘要翻译：固态成像系统具有至少一个具有第一和第二系列像素的CMOS成像器，其中一系列的像素相对于另一系列的像素偏移，即交错。多个成像器可以端对端排列，跨接线连接像素输出导体或每个像素，以便像素馈送到每个系列的公共输出放大器，以最小化芯片到芯片的偏移电压。像素可以彼此对角地偏移，并且可以构造彩色成像器，其中色带滤光器对角地布置在成像区域上。这种布置使颜色串扰最小化。位于微透镜阵列中，每个微透镜覆盖多个像素。每个微透镜下的不同像素可以沿对角线对齐。相同微透镜下的不同像素可以具有不同的积分时间，以增加成像器的动态范围。

7. 发明申请

US20060045504A1 Method and apparatus for controlling a lens, and camera module incorporating same 失效
公开(公告)号：US20060045504A1
公开(公告)日：2006-03-02
申请号：US11210022
申请日：2005-08-22
申请人： Terry Zarnowski , Jeffrey Zarnowski , Iain Neil
发明人： Terry Zarnowski , Jeffrey Zarnowski , Iain Neil
IPC分类号： G03B17/00
CPC分类号： H04N5/23212 , G02B7/028 , G02B7/102 , G02B13/12 , G02B27/646 , G03B17/02 , H04N5/23248 , H04N5/23287 , H04N5/2354
摘要： An efficient image capture system is disclosed that integrates functions to control a lens including one or more of focus or object distance, zoom, temperature compensation, and stabilization within an image signal processor (ISP) with appropriate algorithms. In particular, the integrated ISP circuitry may control the motion of the focus and zoom optics of an optical assembly, control stabilization, control the flash, provide enhanced functions and features for controlling the zoom and focus lenses to enable enhanced image capture sequences and/or tracking lens data, provide a set of algorithms within the ISP to alter the aspect ratio (both height and width of an image) of the image, for example to compensate for the addition of an anamorphic lens, and integrate an anamorphic lens into the module to alter an image's projected aspect ratio onto the focal plane array.

8. 发明申请

US20060202107A1 SCANNING IMAGER EMPLOYING MULTIPLE CHIPS WITH STAGGERED PIXELS 有权
标题翻译：扫描图像使用多个像素使用多个图像
公开(公告)号：US20060202107A1
公开(公告)日：2006-09-14
申请号：US11434666
申请日：2006-05-16
申请人： Jeffrey Zarnowski , Ketan Karia , Michael Joyner , Thomas Poonnen
发明人： Jeffrey Zarnowski , Ketan Karia , Michael Joyner , Thomas Poonnen
IPC分类号： H01L27/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14621 , H01L27/14625 , H01L27/14643 , H01L27/14645 , H04N1/03 , H04N1/0308 , H04N1/1933 , H04N1/1934 , H04N5/3692
摘要： A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk.
摘要翻译：固态成像系统具有至少一个具有第一和第二系列像素的CMOS成像器，其中一系列的像素相对于另一系列的像素偏移，即交错。多个成像器可以端对端排列，跨接线连接像素输出导体或每个像素，以便像素馈送到每个系列的公共输出放大器，以最小化芯片到芯片的偏移电压。像素可以彼此对角地偏移，并且可以构造彩色成像器，其中色带滤光器对角地布置在成像区域上。这种布置使颜色串扰最小化。

9. 发明申请

US20060012696A1 Image sensor ADC and CDS per column 有权
公开(公告)号：US20060012696A1
公开(公告)日：2006-01-19
申请号：US11230385
申请日：2005-09-20
申请人： Jeffrey Zarnowski , Ketan Karia , Thomas Poonnen
发明人： Jeffrey Zarnowski , Ketan Karia , Thomas Poonnen
IPC分类号： H04N3/14
CPC分类号： H04N5/335 , H03M1/1019 , H03M1/123 , H03M1/1235 , H03M1/56 , H04N5/3742 , H04N5/37455 , H04N5/3765 , H04N5/378
摘要： A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. An N-bit counter supplies an N-bit DAC to produce an analog ramp output with a level that varies corresponding to the contents of the counter. A ripple counter or equivalent is associated with each respective column. A clock supplies clock signals to the counter elements. A comparator in each column gates the counter element when the analog ramp equals the pixel value for that column. The contents of the counters are transferred sequentially to a video output bus to produce the digital video signal. Additional black-level readout counter elements can create and store a digital value that corresponds to a dark or black video level. A subtraction element subtracts the black level value from the pixel value to reduce fixed pattern noise. An additional array of buffer counter/latches can be employed. The ripple counters can be configured as counters to capture the digital video level, and then as shift registers to clock out the video levels to an output bus. The clock pulses for the DAC counter and for the ripple counters can be at the same or different rates.

10. 发明授权

US06693270B2 Current mode analog signal multiplexing bus and a method thereof 有权
标题翻译：电流模式信号复用总线及其方法
公开(公告)号：US06693270B2
公开(公告)日：2004-02-17
申请号：US10016147
申请日：2001-10-26
申请人： Robert Iodice , Matthew Pace , Jeffrey Zarnowski
发明人： Robert Iodice , Matthew Pace , Jeffrey Zarnowski
IPC分类号： H01L2700
CPC分类号： H04N5/378 , H04N5/365 , H04N5/3742 , H04N5/37457
摘要： A bus system which includes two or more voltage-to-current transformers, a common bus, a terminal bus coupled to a voltage source, two or more first switches, and a selection circuit. Each of the voltage-to-current transformers converts a voltage signal to a current signal. The common bus carries the current signals from the voltage-to-current transformers to an output bus. Each of the first switches has a first position where an output from one of the voltage-to-current transformers is coupled to the common bus and a second position where the output is coupled to the terminal bus. The selection circuit is coupled to each of the first switches and controls movement of each of the first switches between the first and second positions.
摘要翻译：一种总线系统，包括两个或更多个电压 - 电流互感器，公共总线，耦合到电压源的终端总线，两个或更多个第一开关和选择电路。每个电压 - 电流互感器将电压信号转换为电流信号。公共总线将电流 - 电流互感器的电流信号传送到输出总线。每个第一开关具有第一位置，其中来自电压 - 电流互感器之一的输出耦合到公共总线，以及第二位置，其中输出耦合到终端总线。选择电路耦合到每个第一开关并控制第一和第二位置之间的每个第一开关的运动。

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