专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06493280B2 Method of reducing trapped holes induced by erase operations in the tunnel oxide of flash memory cells 有权
公开(公告)号：US06493280B2
公开(公告)日：2002-12-10
申请号：US09982682
申请日：2001-10-22
申请人： Andrei Mihnea , Jeffrey Kessenich , Chun Chen
发明人： Andrei Mihnea , Jeffrey Kessenich , Chun Chen
IPC分类号： G11C700
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , G11C16/3445
摘要： A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.

2. 发明授权

US07952936B2 Program-verify method 有权
标题翻译：程序验证方法
公开(公告)号：US07952936B2
公开(公告)日：2011-05-31
申请号：US12606828
申请日：2009-10-27
申请人： Andrei Mihnea , Todd Marquart , Jeffrey Kessenich
发明人： Andrei Mihnea , Todd Marquart , Jeffrey Kessenich
IPC分类号： G11C16/06
CPC分类号： G11C8/12 , G11C8/08 , G11C16/0483 , G11C16/3454 , G11C16/3459
摘要： Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations.
摘要翻译：公开了一些方法和装置，一些这样的方法包括将验证直通电压施加到浮动栅极存储器阵列的未选择的选择线，其大于施加到未选择的选择线的读取直通电压。其他方法涉及在程序验证操作中利用单元电流读取来自一个或多个存储器单元的值，该单元电流低于用于在读取操作中从一个或多个存储器单元读取值的单元电流。

3. 发明申请

US20070014158A1 Flash memory device with improved programming performance 有权
标题翻译：具有改进编程性能的闪存设备
公开(公告)号：US20070014158A1
公开(公告)日：2007-01-18
申请号：US11522600
申请日：2006-09-18
申请人： Jeffrey Kessenich
发明人： Jeffrey Kessenich
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C8/08 , G11C16/08 , G11C16/10
摘要： A selected word line that is coupled to a cell to be programmed is biased during a program operation. The unselected word lines are biased with a negative potential to reduce the cell leakage at programming bit line potential. A programming pulse is applied to the bit line coupled to the cell to be programmed. During verification, the unselected word lines are biased back to ground potential.
摘要翻译：耦合到要编程的单元的所选字线在编程操作期间被偏置。未选择的字线偏置负电位以减少编程位线电位下的单元泄漏。将编程脉冲施加到耦合到要编程的单元的位线。在验证期间，未选择的字线被偏置回地电位。

4. 发明授权

US07619931B2 Program-verify method with different read and verify pass-through voltages 有权
标题翻译：具有不同读取和验证直通电压的程序验证方法
公开(公告)号：US07619931B2
公开(公告)日：2009-11-17
申请号：US11821914
申请日：2007-06-26
申请人： Andrei Mihnea , Todd Marquart , Jeffrey Kessenich
发明人： Andrei Mihnea , Todd Marquart , Jeffrey Kessenich
IPC分类号： G11C16/06
CPC分类号： G11C8/12 , G11C8/08 , G11C16/0483 , G11C16/3454 , G11C16/3459
摘要： Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading value from one or more memory cells in read operations.
摘要翻译：公开了方法和装置，这样的方法包括将验证直通电压施加到浮选存储器阵列的未选择的选择线，该选择线大于施加到未选择的选择线的读通过电压。其他方法涉及利用单元电流来读取来自读取操作中的一个或多个存储器单元的值的单元电流低于程序验证操作中的一个或多个存储器单元的值。

5. 发明申请

US20060146611A1 Flash memory device with improved programming performance 有权
公开(公告)号：US20060146611A1
公开(公告)日：2006-07-06
申请号：US11367922
申请日：2006-03-03
申请人： Jeffrey Kessenich
发明人： Jeffrey Kessenich
IPC分类号： G11C16/04
CPC分类号： G11C8/08 , G11C16/08 , G11C16/10
摘要： A selected wordline that is coupled to a cell to be programmed is biased during a program operation. The unselected wordlines are biased with a negative potential to reduce the cell leakage at programming bitline potential. A programming pulse is applied to the bitline coupled to the cell to be programmed. During verification, the unselected wordlines are biased back to ground potential.

6. 发明授权

US06426898B1 Method of reducing trapped holes induced by erase operations in the tunnel oxide of flash memory cells 有权
标题翻译：减少由闪存单元的隧道氧化物中的擦除操作引起的被捕获的空穴的方法
公开(公告)号：US06426898B1
公开(公告)日：2002-07-30
申请号：US09797682
申请日：2001-03-05
申请人： Andrei Mihnea , Jeffrey Kessenich , Chun Chen
发明人： Andrei Mihnea , Jeffrey Kessenich , Chun Chen
IPC分类号： G11C700
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , G11C16/3445
摘要： A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.
摘要翻译：公开了一种擦除闪存器件中的存储单元的方法，该闪速存储器件将通过隧道氧化物的电子重新捕获隧道氧化物中的空穴（在擦除操作之后）。该方法使用擦除操作，擦除所有进行擦除操作的存储单元。对过度消耗的细胞进行细胞愈合操作。愈合操作使电子通过隧道氧化物并与被捕获的孔重组。该复合基本上减少了隧道氧化物内的被捕获的孔，而不降低擦除操作的速度。此外，通过减少捕获的空穴，闪存单元的电荷保持率，总体性能和耐久性显着增加。

7. 发明申请

US20100046303A1 PROGRAM-VERIFY METHOD 有权
标题翻译：程式验证方法
公开(公告)号：US20100046303A1
公开(公告)日：2010-02-25
申请号：US12606828
申请日：2009-10-27
申请人： Andrei Mihnea , Todd Marquart , Jeffrey Kessenich
发明人： Andrei Mihnea , Todd Marquart , Jeffrey Kessenich
IPC分类号： G11C16/06
CPC分类号： G11C8/12 , G11C8/08 , G11C16/0483 , G11C16/3454 , G11C16/3459
摘要： Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations.
摘要翻译：公开了一些方法和装置，一些这样的方法包括将验证直通电压施加到浮动栅极存储器阵列的未选择的选择线，其大于施加到未选择的选择线的读取直通电压。其他方法涉及在程序验证操作中利用单元电流读取来自一个或多个存储器单元的值，该单元电流低于用于在读取操作中从一个或多个存储器单元读取值的单元电流。

8. 发明申请

US20050248990A1 Flash memory device with improved programming performance 有权
标题翻译：具有改进编程性能的闪存设备
公开(公告)号：US20050248990A1
公开(公告)日：2005-11-10
申请号：US10841785
申请日：2004-05-07
申请人： Jeffrey Kessenich
发明人： Jeffrey Kessenich
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C8/08 , G11C16/08 , G11C16/10
摘要： A selected wordline that is coupled to a cell to be programmed is biased during a program operation. The unselected wordlines are biased with a negative potential to reduce the cell leakage at programming bitline potential. A programming pulse is applied to the bitline coupled to the cell to be programmed. During verification, the unselected wordlines are biased back to ground potential.
摘要翻译：耦合到要编程的单元的选定字线在编程操作期间被偏置。未选择的字线偏向负电位，以减少编程位线电位下的电池泄漏。将编程脉冲施加到耦合到要编程的单元的位线。在验证期间，未选择的字线被偏回到地电位。

9. 发明申请

US20090003078A1 Program-verify method 有权
标题翻译：程序验证方法
公开(公告)号：US20090003078A1
公开(公告)日：2009-01-01
申请号：US11821914
申请日：2007-06-26
申请人： Andrei Mihnea , Todd Marquart , Jeffrey Kessenich
发明人： Andrei Mihnea , Todd Marquart , Jeffrey Kessenich
IPC分类号： G11C11/34
CPC分类号： G11C8/12 , G11C8/08 , G11C16/0483 , G11C16/3454 , G11C16/3459
摘要： Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading value from one or more memory cells in read operations.
摘要翻译：公开了方法和装置，这样的方法包括将验证直通电压施加到浮选存储器阵列的未选择的选择线，该选择线大于施加到未选择的选择线的读通过电压。其他方法涉及利用单元电流来读取来自读取操作中的一个或多个存储器单元的值的单元电流低于程序验证操作中的一个或多个存储器单元的值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式