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1. 发明授权

US06467012B1 Method and apparatus using a distributed system structure to support bus-based cache-coherence protocols for symmetric multiprocessors 失效
标题翻译：使用分布式系统结构来支持对称多处理器的基于总线的高速缓存相干协议的方法和装置
公开(公告)号：US06467012B1
公开(公告)日：2002-10-15
申请号：US09350031
申请日：1999-07-08
申请人： Manuel Alvarez , Sanjay Raghunath Deshpande , Peter Dau Geiger , Jeffrey Holland Gruger
发明人： Manuel Alvarez , Sanjay Raghunath Deshpande , Peter Dau Geiger , Jeffrey Holland Gruger
IPC分类号： G06F1300
CPC分类号： G06F12/0813 , G06F12/0811
摘要： A method and apparatus for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. Each of the processors may have multiple caches. The address switch connects to each of the node controllers and to each of the memory subsystems, and each of the memory subsystems connects to the address switch and to each of the node controllers. The node controller receives commands from a master device and queues commands received from a master device. The node controller has a deterministic delay between latching a snooped command broadcast by the address switch and presenting the command to the master devices on the node controller's master device buses. The memory subsystems contain a memory controller and a fixed delay pipe from the address port to the memory controller so that the memory subsystem has a deterministic delay between receiving a command from the address switch and presenting the command to the memory controller. The buses between the master devices, the node controllers, the address switch, and the memory subsystems are operable using a variety of bus protocols.
摘要翻译：提供了一种使用基于总线的高速缓存相干协议的大方向对称多处理器系统的方法和装置。分布式系统结构包含地址交换机，多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备，处理器，I / O代理或相干存储器适配器。每个处理器可以具有多个高速缓存。地址开关连接到每个节点控制器和每个存储器子系统，并且每个存储器子系统连接到地址开关和每个节点控制器。节点控制器从主设备接收命令，并对从主设备接收的命令进行排队。节点控制器在锁存由地址开关广播的窥探命令之间并且将命令呈现给节点控制器主设备总线上的主设备时具有确定性的延迟。存储器子系统包含存储器控制器和从地址端口到存储器控制器的固定延迟管，使得存储器子系统在从地址开关接收命令并将命令呈现给存储器控制器之间具有确定性的延迟。主设备，节点控制器，地址交换机和存储器子系统之间的总线可以使用各种总线协议来操作。

2. 发明授权

US5784394A Method and system for implementing parity error recovery schemes in a data processing system 失效
标题翻译：在数据处理系统中实现奇偶校验错误恢复方案的方法和系统
公开(公告)号：US5784394A
公开(公告)日：1998-07-21
申请号：US749250
申请日：1996-11-15
申请人： Manuel Joseph Alvarez, II , Gary Dale Carpenter , Kai Cheng , Jeffrey Holland Gruger , Jin Chin Wang
发明人： Manuel Joseph Alvarez, II , Gary Dale Carpenter , Kai Cheng , Jeffrey Holland Gruger , Jin Chin Wang
IPC分类号： G06F11/10 , G06F12/08 , H03M13/00
CPC分类号： G06F12/082 , G06F11/1008 , G06F11/108
摘要： A method and apparatus in a data processing system having a plurality of node controllers and a memory unit for each of the node controllers. Each one of the node controllers including at least one processor having a cache. Each memory unit including a plurality of entries each having an exclusive bit, an address tag, and an inclusion field. Each bit of the inclusion field representing one of the node controllers. The method and apparatus allow error recovery for errors occurring within the entries without using the ECC implementation. Specifically, two parity bits are used for detecting errors within an entry and logic for flushing any cache lines represented by the entry in error. The method and apparatus also includes means for detecting persistent errors and for indicating whether the error is generated by either hardware or software.
摘要翻译：一种数据处理系统中的方法和装置，具有多个节点控制器和每个节点控制器的存储单元。每个节点控制器包括具有高速缓存的至少一个处理器。每个存储器单元包括多个条目，每个条目具有排他位，地址标签和包含字段。包含字段的每一位表示节点控制器之一。该方法和装置允许在条目中发生的错误的错误恢复，而不使用ECC实现。具体来说，两个奇偶校验位用于检测条目中的错误和逻辑，用于刷新由错误条目表示的任何高速缓存行。所述方法和装置还包括用于检测持久性错误并用于指示所述错误是由硬件还是软件产生的装置。

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