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1. 发明授权

US5261046A Resequencing line store device 失效
标题翻译：重新排序线路存储设备
公开(公告)号：US5261046A
公开(公告)日：1993-11-09
申请号：US774141
申请日：1991-10-15
申请人： Gary W. Shope , Jeffrey A. Small
发明人： Gary W. Shope , Jeffrey A. Small
IPC分类号： G06F7/78 , G06K15/12 , H04N1/193 , G06F3/14 , H04N1/00
CPC分类号： G06F7/78 , G06K15/1247 , H04N1/1931
摘要： An image recording apparatus with inexpensive data line resequencing circuitry for formatting image signals to a print head. The circuitry includes a resequencing line store device connectable to a data link and a control link for resequencing at least one first line of sequentially ordered data bits carried by the data link according to control signals carried by the control link. The resequencing line store device includes a plurality of interconnected memory cells operable for storage and selectable transfer of the data bits in response to the control signals, whereby the plurality of cells are arranged in a plurality of cell groups and a plurality of cell subgroups corresponding respectively to groups and subgroups of the bits. The bits may be shifted into the plurality of groups in sequential order and shifted from the plurality of cell subgroups in a non-sequential order corresponding to the first and second partitions.
摘要翻译：一种图像记录装置，具有用于将图像信号格式化到打印头的廉价数据线重新排序电路。电路包括可连接到数据链路的重新排序线路存储设备和控制链路，用于根据由控制链路携带的控制信号来重新排序由数据链路承载的至少一行第一行顺序排列的数据位。重新排序行存储装置包括多个互连的存储器单元，可操作用于响应于控制信号而存储和选择性地传送数据位，由此多个单元被分别布置在多个单元组中，并且多个单元子组分别对应到组的组和子组的位。这些位可以按顺序移位到多个组中，并且以对应于第一和第二分区的非顺序顺序从多个单元子组移位。

2. 发明授权

US5241222A Dram interface adapter circuit 失效
标题翻译： DRAM接口适配器电路
公开(公告)号：US5241222A
公开(公告)日：1993-08-31
申请号：US810978
申请日：1991-12-20
申请人： Jeffrey A. Small , Alan T. Torok
发明人： Jeffrey A. Small , Alan T. Torok
IPC分类号： G06F12/02 , G06F12/04 , G11C7/22 , G11C11/401
CPC分类号： G11C7/22
摘要： The present invention is an interface adapter circuit that allows multiple types of 256K by 16 bit dynamic random random access memories to be used by system manufacturers. The interface adapter circuit selects a type of outputs signal set to produce responsive to a mode selection signal. The circuit converts an input signal set including a column address probe and low and high by write signals into either a first output signal set, including one column address strobe and high and low byte write signals, or a second output signal set including a single write signal and high and low column address signals, responsive to the selection signal. The circuit includes a logic circuit for producing the signals and flip flops for holding the signal produced. The flip flops also synchronize other memory address, etc. signals with the signals produced by the adapter circuit. The interface adapter circuit can also convert write nd column address timing signals and low and high byte write signals into the two sets responsive to a selection signal.

3. 发明授权

US5157495A Multi-mode video standard selection circuit and selection method 失效
标题翻译：多模式视频标准选择电路及选择方法
公开(公告)号：US5157495A
公开(公告)日：1992-10-20
申请号：US811524
申请日：1991-12-20
申请人： Jeffrey A. Small
发明人： Jeffrey A. Small
IPC分类号： H04N9/80 , H04N5/46
CPC分类号： H04N5/46
摘要： A first embodiment of the present invention provides logic to select between one of three or more user entered video standards and one or more selectable default video standards. The logic overrides the default standard with the user selected standard. A second embodiment includes a state machine that sets a mode output to a default standard from among two or more standards specified at the factory using jumper pins. The state machine can step through the two or more available standard modes, thereby changing the picture displayed to the user and, as desired, allowing the user to indicate what standard should be used.

4. 发明授权

US5126759A Non-impact printer with token bit control of data and current regulation signals 失效
标题翻译：无冲击打印机，具有数据和电流调节信号的令牌位控制
公开(公告)号：US5126759A
公开(公告)日：1992-06-30
申请号：US543930
申请日：1990-06-26
申请人： Jeffrey A. Small , Mary A. Hadley , Martin Potucek , Hieu T. Pham
发明人： Jeffrey A. Small , Mary A. Hadley , Martin Potucek , Hieu T. Pham
IPC分类号： B41J2/45
CPC分类号： B41J2/45
摘要： An LED printhead or the like includes a data bus for carrying multibit digital image data signals for grey level recording. A token bit signal is generated and shifted through registers upon the printhead to enable image data registers associated with each LED to latch the image data signals in appropriate order. The image data signals control the energization times for recording pixels. A digitally adjustable current mirror controls the level of current to each LED during recording. Digital current data signals for controlling this level of current are also communicated over one of the lines of the data bus. A token bit signal is also used to control the latching of current data signals in registers storing the digital data used for current control.
摘要翻译： LED打印头等包括用于承载用于灰度级记录的多位数字图像数据信号的数据总线。生成令牌位信号并通过打印头上的寄存器移位，以使与每个LED相关联的图像数据寄存器以适当的顺序锁定图像数据信号。图像数据信号控制记录像素的通电时间。数字可调电流镜在录制过程中控制每个LED的电流电平。用于控制该电流电平的数字电流数据信号也通过数据总线的一条线路传送。令牌位信号也用于控制存储用于电流控制的数字数据的寄存器中的当前数据信号的锁存。

5. 发明授权

US4922137A Programmable sequence generator 失效
标题翻译：可编程序列发生器
公开(公告)号：US4922137A
公开(公告)日：1990-05-01
申请号：US362293
申请日：1989-06-06
申请人： Jeffrey A. Small , Mark D. Brown , John A. Vincent
发明人： Jeffrey A. Small , Mark D. Brown , John A. Vincent
IPC分类号： H03K19/177
CPC分类号： H03K19/1772
摘要： A programmable, UV erasable integrated circuit for the generation of various timing sequences. It includes one AND plane, two OR planes, scan path pipeline registers to allow programming and reading, two counters, and a block of high speed logic which runs at an integer multiple of the clock rate of the pipeline registers. The high speed logic also includes a means for smoothly adjusting the positions of various edges of output signals by changing external resistors.
摘要翻译：一种用于生成各种定时序列的可编程UV可擦除集成电路。它包括一个AND平面，两个OR平面，扫描路径流水线寄存器以允许编程和读取，两个计数器，以及以流水线寄存器的时钟速率的整数倍运行的高速逻辑块。高速逻辑还包括通过改变外部电阻器来平滑地调整输出信号的各个边缘的位置的装置。

6. 发明授权

US09665214B2 System and methods for determining object information using selectively floated electrodes 有权
公开(公告)号：US09665214B2
公开(公告)日：2017-05-30
申请号：US13434608
申请日：2012-03-29
申请人： Tom R. Vandermeijden , Jeffrey A. Small
发明人： Tom R. Vandermeijden , Jeffrey A. Small
IPC分类号： G06F3/044 , G06F3/041
CPC分类号： G06F3/044 , G06F3/0414
摘要： The embodiments described herein provide devices and methods that facilitate improved sensor devices. In one embodiment, a capacitive input device is provided that includes a processing system, a plurality of sensing electrodes configured to sense objects in a sensing region, a conductor, and a shield layer comprising at least one shield electrode, where the at least one shield electrode is disposed between the plurality of sensing electrodes and the conductor. The processing system is configured to operate in a first mode and a second mode. When operating in the first mode the processing system is configured to determine position information for objects in the sensing region using the plurality of sensing electrodes. When operating in a second mode the processing system is configured to electrically float the at least one shield electrode and to determine force information for objects in the sensing region using the plurality of sensing electrodes.

7. 发明申请

US20120111119A1 METHOD AND APPARATUS FOR SENSING AN INPUT OBJECT RELATIVE TO A SENSING REGION OF AN ULTRASOUND SENSOR DEVICE 有权
标题翻译：用于感测与超声波传感器装置的感测区域相关的输入对象的方法和装置
公开(公告)号：US20120111119A1
公开(公告)日：2012-05-10
申请号：US13289732
申请日：2011-11-04
申请人： Jeffrey A. Small , Clyde Washburn
发明人： Jeffrey A. Small , Clyde Washburn
IPC分类号： G01N29/00
CPC分类号： G06F3/0436 , G06F3/0412
摘要： A subsystem, system and method for sensing an input object relative to a sensing region of an ultrasound sensor device are disclosed herein. In one embodiment, a subsystem for sensing an input object relative to a sensing region of an ultrasound sensor device includes a circuit, a switch coupled to an output of the circuit, and an integrating capacitor coupled to the output of the circuit. The circuit has an input for receiving a resulting signal comprising positive and negative polarities, the resulting signal having effects indicative of the input object relative to the sensing region. The integrating capacitor is also coupled to a substantially constant voltage source and to the switch. The circuit is operable to output a rectified signal to the first integrating capacitor indicative of the input object relative to a sensing region.
摘要翻译：本文公开了一种用于感测相对于超声波传感器装置的感测区域的输入物体的子系统和系统。在一个实施例中，用于感测相对于超声传感器装置的感测区域的输入物体的子系统包括电路，耦合到电路的输出的开关以及耦合到电路的输出的积分电容器。电路具有用于接收包括正和负极性的结果信号的输入，所得到的信号具有指示输入对象相对于感测区域的效果。积分电容器还耦合到基本恒定的电压源和开关。电路可操作以将整流信号输出到指示输入物体相对于感测区域的第一积分电容器。

8. 发明授权

US08018176B1 Selectable power FET control for display power converter 有权
标题翻译：显示功率转换器可选功率FET控制
公开(公告)号：US08018176B1
公开(公告)日：2011-09-13
申请号：US11770539
申请日：2007-06-28
申请人： Jeffrey A. Small , Anirudh Oberoi
发明人： Jeffrey A. Small , Anirudh Oberoi
IPC分类号： H05B37/02
CPC分类号： H02M3/156 , G09G2330/028
摘要： A chip-on-glass (COG) display driver comprises a direct current to direct current converter (DC-DC) converter that uses “off-glass” and/or “off-chip” inductive/capacitive (LC) components. The DC-DC converter can be configured to use either an internal or external switch (such as a power FET) in response to a mode signal. Selection of an internal or external mode allows a single converter chip design to be optimized for various applications.
摘要翻译：玻璃（COG）显示驱动器包括使用“脱玻璃”和/或“片外”电感/电容（LC）组件的直流电流转换器（DC-DC）转换器。 DC-DC转换器可以配置为响应于模式信号使用内部或外部开关（例如功率FET）。选择内部或外部模式允许单个转换器芯片设计针对各种应用进行优化。

9. 发明授权

US07755662B2 Digital camera providing image processing for an attachable printer 有权
标题翻译：数码相机为可连接打印机提供图像处理
公开(公告)号：US07755662B2
公开(公告)日：2010-07-13
申请号：US11680682
申请日：2007-03-01
申请人： Kenneth A. Parulski , Jeffrey A. Small , Douglas W. Couwenhoven , Jason C. VanBlargan , Raymond E. Wess
发明人： Kenneth A. Parulski , Jeffrey A. Small , Douglas W. Couwenhoven , Jason C. VanBlargan , Raymond E. Wess
IPC分类号： H04N5/225 , H04N1/60 , B41J3/00
CPC分类号： H04N5/225 , H04N1/00278 , H04N1/00962 , H04N1/2112 , H04N1/2158 , H04N1/32128 , H04N2101/00 , H04N2201/001 , H04N2201/0049 , H04N2201/0053 , H04N2201/0055 , H04N2201/0082 , H04N2201/0086 , H04N2201/3242 , H04N2201/3274 , H04N2201/3278
摘要： A digital imaging system is provided that includes a digital camera and a color printer. The digital camera comprises: a housing; an image sensor adapted to capture analog image data; an analog-to-digital converter adapted to convert the analog image data; an image processor adapted to perform first processing and compression of the digital image data to create a first-processed digital image file; a digital memory in the camera housing having a plurality of the first-processed digital image files stored in the digital memory; and a color printer interface to which a digital image file, which is selected from the digital memory, is applied. The color printer comprises: a color-marking apparatus, and a digital camera interface, wherein the image processor in the digital camera is adapted to perform second processing on the selected digital image file before the selected digital image file is applied.
摘要翻译：提供了一种包括数码相机和彩色打印机的数字成像系统。该数码相机包括：一个外壳; 适于捕获模拟图像数据的图像传感器; 适于转换模拟图像数据的模拟 - 数字转换器; 适于执行数字图像数据的第一处理和压缩以创建第一处理的数字图像文件的图像处理器; 相机外壳中的数字存储器具有存储在数字存储器中的多个第一处理数字图像文件; 以及应用了从数字存储器中选择的数字图像文件的彩色打印机接口。彩色打印机包括：彩色打标设备和数字照相机接口，其中数字照相机中的图像处理器适于在所选择的数字图像文件被应用之前对所选择的数字图像文件执行第二处理。

10. 发明授权

US07268790B1 Display system with framestore and stochastic dithering 有权
标题翻译：显示系统与帧存储和随机抖动
公开(公告)号：US07268790B1
公开(公告)日：2007-09-11
申请号：US10230975
申请日：2002-08-29
申请人： Jeffrey A. Small , Christopher A. Ludden
发明人： Jeffrey A. Small , Christopher A. Ludden
IPC分类号： G09G5/02
CPC分类号： G09G5/393 , G09G3/2048 , G09G5/395 , G09G2320/0276
摘要： A display system provides temporal stochastic dithering to image data for storage in a frame buffer for display. Stochastic dithering is used to reduce the size of the frame buffer and the complexity of the drive circuitry that is used to display an image in accordance with the image data. The bit depth of the frame buffer is reduced by spatially dithering image data for the image data before the image data is written into the frame buffer. Additionally, the displayed image is temporally dithered by using a different dither pattern for successive frames. Uncorrelated stochastic dither patterns are used to minimize detection of the dither patterns within the displayed image.
摘要翻译：显示系统为图像数据提供时间随机抖动，以存储在用于显示的帧缓冲器中。随机抖动用于减小帧缓冲器的大小以及用于根据图像数据显示图像的驱动电路的复杂性。在将图像数据写入帧缓冲器之前，通过用于图像数据的空间抖动图像数据来减少帧缓冲器的位深度。此外，通过对连续的帧使用不同的抖动图案，显示的图像在时间上被抖动。使用不相关的随机抖动图案来最小化显示图像内的抖动图案的检测。

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