专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09093499B2 Integrated circuit using FDSOI technology, with well sharing and means for biasing oppositely doped ground planes present in a same well 有权
标题翻译：使用FDSOI技术的集成电路，具有良好的共享和用于偏置存在于同一井中的相反掺杂的接地平面的装置
公开(公告)号：US09093499B2
公开(公告)日：2015-07-28
申请号：US13627059
申请日：2012-09-26
申请人： Jean-Philippe Noel , Bastien Giraud , Olivier Thomas
发明人： Jean-Philippe Noel , Bastien Giraud , Olivier Thomas
IPC分类号： H01L29/66 , H01L29/786 , H01L21/768 , H01L21/84 , H01L27/12 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/768 , H01L21/823892 , H01L21/84 , H01L27/0928 , H01L27/1203 , H01L29/78609 , H01L29/78648
摘要： A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.
摘要翻译：一种制造方法包括：IC，其包括半导体衬底，掩埋绝缘层和半导体层的堆叠;形成在半导体层中和/或上的半导体层的第一电子部件;产生第一偏置电压的偏置电路;第一和第二偏置电路施加与第一偏置电压相同的偏置电压的通孔型互连，将第一电子部件与第一和第二互连分开的第一绝缘沟槽，具有第一类型的掺杂的第一接地平面在第一电子部件的埋置绝缘层铅垂之下，并且在第一绝缘沟槽下方延伸并且与第一互连接触，并且具有与第一类型相反的第二类型掺杂的第一阱具有第一接地层并且在第一绝缘沟槽下方延伸并与第二互连接触。

2. 发明授权

US08311518B2 Method and system for executing applications in wireless telecommunication networks 有权
标题翻译：在无线电信网络中执行应用的方法和系统
公开(公告)号：US08311518B2
公开(公告)日：2012-11-13
申请号：US12111860
申请日：2008-04-29
申请人： Nicolas Philippe Fiorini , Jean-Philippe Noel
发明人： Nicolas Philippe Fiorini , Jean-Philippe Noel
IPC分类号： H04M3/42
CPC分类号： H04L67/34 , H04L67/02 , H04L67/26
摘要： A method and system allow a mobile device user to automatically execute a service application to provide a requested service. The user may enter a USSD code or initiate a voice call to a special number. The wireless network recognizes the user's act as a request for a specific service and notifies the service provider. The service provider sends an activation command to the mobile device and may also initiate installing the service application.
摘要翻译：方法和系统允许移动设备用户自动执行服务应用以提供所请求的服务。用户可以输入USSD代码或发起对特殊号码的语音呼叫。无线网络将用户的行为识别为对特定服务的请求，并通知服务提供商。服务提供商向移动设备发送激活命令，并且还可以启动安装服务应用。

3. 发明申请

US20120126333A1 SELF-CONTAINED INTEGRATED CIRCUIT HAVING TRANSISTORS WITH SEPARATE THRESHOLD VOLTAGES 有权
标题翻译：具有独立阈值电压的具有晶体管的自包含集成电路
公开(公告)号：US20120126333A1
公开(公告)日：2012-05-24
申请号：US13262376
申请日：2010-04-01
申请人： Olivier Thomas , Jean-Philippe Noel
发明人： Olivier Thomas , Jean-Philippe Noel
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/84 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/1203
摘要： The invention relates to an integrated circuit including an active semiconducting layer separated from a semiconducting substrate layer by an embedded insulating material surface, including: first and second transistors (205, 213) of a single type; first and second floorplans arranged vertically perpendicular to the first and second transistors; wherein the first transistor has a doping of the floorplan thereof, opposite that of the source thereof, and a first threshold voltage; the second transistor has a doping of the floorplan thereof, identical to that of the source thereof, and a second threshold voltage; the first threshold voltage is dependent on the potential difference applied between the source and the floorplan of the first transistor; and the second threshold voltage is dependent on the potential difference applied between the source and the floorplan of the second transistor.
摘要翻译：本发明涉及一种集成电路，其包括通过嵌入式绝缘材料表面与半导体衬底层分离的有源半导体层，其包括：单一类型的第一和第二晶体管（205,213）; 垂直于第一和第二晶体管垂直排列的第一和第二平面图; 其中所述第一晶体管具有与其源极相反的其平面图的掺杂和第一阈值电压; 第二晶体管具有与其源极相同的其平面图的掺杂和第二阈值电压; 第一阈值电压取决于施加在第一晶体管的源极和平面布置图之间的电位差; 并且第二阈值电压取决于施加在第二晶体管的源极和平面布置图之间的电位差。

4. 发明申请

US20090270077A1 METHOD AND SYSTEM FOR EXECUTING APPLICATIONS IN WIRELESS TELECOMMUNICATION NETWORKS 有权
标题翻译：在无线电信网络中执行应用的方法和系统
公开(公告)号：US20090270077A1
公开(公告)日：2009-10-29
申请号：US12111860
申请日：2008-04-29
申请人： Nicolas Philippe FIORINI , Jean-Philippe Noel
发明人： Nicolas Philippe FIORINI , Jean-Philippe Noel
IPC分类号： H04M3/42
CPC分类号： H04L67/34 , H04L67/02 , H04L67/26
摘要： A method and system allow a mobile device user to automatically execute a service application to provide a requested service. The user may enter a USSD code or initiate a voice call to a special number. The wireless network recognizes the user's act as a request for a specific service and notifies the service provider. The service provider sends an activation command to the mobile device and may also initiate installing the service application.
摘要翻译：方法和系统允许移动设备用户自动执行服务应用以提供所请求的服务。用户可以输入USSD代码或发起对特殊号码的语音呼叫。无线网络将用户的行为识别为对特定服务的请求，并通知服务提供商。服务提供商向移动设备发送激活命令，并且还可以启动安装服务应用。

5. 发明授权

US08969967B2 Self-contained integrated circuit including adjacent cells of different types 有权
标题翻译：独立的集成电路，包括不同类型的相邻单元
公开(公告)号：US08969967B2
公开(公告)日：2015-03-03
申请号：US14118955
申请日：2012-05-22
申请人： Jean-Philippe Noel , Bastien Giraud , Olivier Thomas
发明人： Jean-Philippe Noel , Bastien Giraud , Olivier Thomas
IPC分类号： H01L27/12 , H01L27/092 , H01L27/11 , H01L21/8238 , H01L21/84 , H01L29/786
CPC分类号： H01L27/092 , H01L21/823878 , H01L21/823892 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/78645
摘要： An integrated circuit includes a stack having a semiconductor substrate with a first type of dopant, an UTBOX type buried insulating layer, electronic components, formed in the substrate, ground planes disposed beneath the buried insulating layer so as to be respectively plumb with corresponding components, wells with the first type of dopant, the wells being respectively beneath corresponding ground planes, and a bias circuit enabling distinct voltages to be applied to the ground planes by the wells. The wells are separated from the substrate by a deep well with a second type of dopant. The wells are separated from each other by a separating structure, which is either a lateral well having a second type of dopant or a block of insulating material.
摘要翻译：一种集成电路包括具有第一种掺杂剂的半导体衬底和形成在衬底中的电子部件的UTBOX型掩埋绝缘层，设置在掩埋绝缘层下方的接地层，以分别为相应的部件，具有第一类型的掺杂剂的阱，阱分别在相应的接地平面之下，以及偏置电路，其使得可以通过阱将不同的电压施加到接地层。孔与衬底通过深阱与第二类型的掺杂剂分离。孔通过分离结构彼此分离，分离结构是具有第二类掺杂剂的侧井或绝缘材料块。

6. 发明授权

US08482070B1 Silicon-on-insulator CMOS integrated circuit with multiple threshold voltages and a method for designing the same 有权
标题翻译：具有多个阈值电压的绝缘体上硅CMOS集成电路及其设计方法
公开(公告)号：US08482070B1
公开(公告)日：2013-07-09
申请号：US13564407
申请日：2012-08-01
申请人： Philippe Flatresse , Bastien Giraud , Jean-Philippe Noel , Matthieu Le Boulaire
发明人： Philippe Flatresse , Bastien Giraud , Jean-Philippe Noel , Matthieu Le Boulaire
IPC分类号： H01L27/092 , H01L21/762 , H01L21/8228 , H01L21/8238
CPC分类号： H01L21/8228 , H01L21/76283 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/1203
摘要： An IC has cells placed in a cell row having a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and an n-doped well beneath it and configured to apply a potential thereto, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and a p-doped well beneath the ground and configured to apply a potential thereto, and cells, each including a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and a p-doped well beneath the ground and configured to apply an electrical potential to the ground, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and an n-doped well beneath the ground and configured to apply a potential thereto. The cells are placed so that pMOS's of standard cells belonging to a row align along it and a transition cell including a another well and contiguous with first row standard cells thus ensuring continuity with wells of those cells.
摘要翻译： IC具有放置在具有包含pMOS下面的接地的UTBOX-FDSOI pMOSFET的单元行中的单元格，以及在其下方的n掺杂阱并且被配置为向其施加电位的单元行，以及包括nMOS下面的地面的UTBOX-FDSOI nMOSFET 和位于地下并被配置为向其施加电位的p掺杂阱，并且每个包括在pMOS下面包括地面的UTBOX-FDSOI pMOSFET的单元和在地下的p掺杂阱并且被配置为施加电以及包含在nMOS之下的地面的UTBOX-FDSOI nMOSFET，以及在地下并被配置为向其施加电位的n掺杂阱。将细胞放置成使得属于一行的pMOS的标准细胞沿着它排列，并且包括另一个阱并且与第一行标准细胞相邻的过渡细胞，从而确保与这些细胞的孔的连续性。

7. 发明授权

US08723267B2 Integrated circuit made out of SOI with transistors having distinct threshold voltages 有权
标题翻译：由具有不同阈值电压的晶体管的SOI制成的集成电路
公开(公告)号：US08723267B2
公开(公告)日：2014-05-13
申请号：US13262376
申请日：2010-04-01
申请人： Olivier Thomas , Jean-Philippe Noel
发明人： Olivier Thomas , Jean-Philippe Noel
IPC分类号： H01L21/70 , H01L21/8238 , H01L27/092 , H01L27/11
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/84 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/1203
摘要： The invention relates to an integrated circuit including an active semiconducting layer separated from a semiconducting substrate layer by an embedded insulating material surface, including: first and second transistors (205, 213) of a single type; first and second floorplans arranged vertically perpendicular to the first and second transistors; wherein the first transistor has a doping of the floorplan thereof, opposite that of the source thereof, and a first threshold voltage; the second transistor has a doping of the floorplan thereof, identical to that of the source thereof, and a second threshold voltage; the first threshold voltage is dependent on the potential difference applied between the source and the floorplan of the first transistor; and the second threshold voltage is dependent on the potential difference applied between the source and the floorplan of the second transistor.
摘要翻译：本发明涉及一种集成电路，其包括通过嵌入式绝缘材料表面与半导体衬底层分离的有源半导体层，其包括：单一类型的第一和第二晶体管（205,213）; 垂直于第一和第二晶体管垂直排列的第一和第二平面图; 其中所述第一晶体管具有与其源极相反的其平面图的掺杂和第一阈值电压; 第二晶体管具有与其源极相同的其平面图的掺杂和第二阈值电压; 第一阈值电压取决于施加在第一晶体管的源极和平面布置图之间的电位差; 并且第二阈值电压取决于施加在第二晶体管的源极和平面布置图之间的电位差。

8. 发明申请

US20130089978A1 INTEGRATED CIRCUIT USING FDSOI TECHNOLOGY, WITH WELL SHARING AND MEANS FOR BIASING OPPOSITELY DOPED GROUND PLANES PRESENT IN A SAME WELL 有权
标题翻译：使用FDSOI技术的集成电路，具有良好的共享和用于偏移相对地面的地面平面的手段
公开(公告)号：US20130089978A1
公开(公告)日：2013-04-11
申请号：US13627059
申请日：2012-09-26
申请人： Jean-Philippe Noel , Bastien Giraud , Olivier Thomas
发明人： Jean-Philippe Noel , Bastien Giraud , Olivier Thomas
IPC分类号： H01L21/768
CPC分类号： H01L21/768 , H01L21/823892 , H01L21/84 , H01L27/0928 , H01L27/1203 , H01L29/78609 , H01L29/78648
摘要： A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.
摘要翻译：一种制造方法包括：IC，其包括半导体衬底，掩埋绝缘层和半导体层的堆叠;形成在半导体层中和/或上的半导体层的第一电子部件;产生第一偏置电压的偏置电路;第一和第二偏置电路施加与第一偏置电压相同的偏置电压的通孔型互连，将第一电子部件与第一和第二互连分开的第一绝缘沟槽，具有第一类型的掺杂的第一接地平面在第一电子部件的埋置绝缘层铅垂之下，并且在第一绝缘沟槽下方延伸并且与第一互连接触，并且具有与第一类型相反的第二类型掺杂的第一阱具有第一接地层并且在第一绝缘沟槽下方延伸并与第二互连接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式