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1. 发明授权

US07266743B2 Combinatorial at-speed scan testing 有权
标题翻译：组合式高速扫描测试
公开(公告)号：US07266743B2
公开(公告)日：2007-09-04
申请号：US11166432
申请日：2005-06-23
申请人： Atul S. Athavale , Jason R. Ng
发明人： Atul S. Athavale , Jason R. Ng
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318594
摘要： A processor including a first distributed shift generator associated with a first time domain, wherein the first distributed shift generator is coupled to a first group of scan chains, the first distributed shift generator to send a shift-enable-flop signal to be received by the first group of scan chains. The processor including a second distributed shift generator associated with a second time domain, wherein the second distributed shift generator is coupled to a second group of scan chains, the second distributed shift generator to send a shift-enable-flop signal to be received by the second group of scan chains. The processor including a scan test controller coupled to the first and second distributed shift generators, the scan test controller to provide clocking signals for the first time domain and the second time domain for performing an at-speed test of circuits coupled to the first group of scan chains.
摘要翻译：一种处理器，包括与第一时域相关联的第一分布式移位发生器，其中所述第一分布式移位发生器耦合到第一组扫描链，所述第一分布式移位发生器发送要由所述第一时域接收的移位使能触发器信号第一组扫描链。所述处理器包括与第二时域相关联的第二分布式移位发生器，其中所述第二分布式移位发生器耦合到第二组扫描链，所述第二分布式移位发生器发送移位使能触发器信号以由第二组扫描链。所述处理器包括耦合到所述第一和第二分布式移位发生器的扫描测试控制器，所述扫描测试控制器提供用于所述第一时域的时钟信号和所述第二时域，用于执行耦合到所述第一组的电路的电路的速度测试扫描链。

2. 发明授权

US07263639B2 Combinatorial at-speed scan testing 有权
标题翻译：组合式高速扫描测试
公开(公告)号：US07263639B2
公开(公告)日：2007-08-28
申请号：US10955615
申请日：2004-09-30
申请人： Atul S. Athavale , Jason R. Ng
发明人： Atul S. Athavale , Jason R. Ng
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318594
摘要： A combinatorial at-speed scan testing. A processor including a plurality of distributed slave counters. Each distributed slave counter coupled to a group of scan chains, each distributed slave counter to generate shift-enable-flop signals to be received by the group of scan chains coupled to each distributed slave counter, the shift-enable-flop signals based at least in part on an external shift-enable signal received by the processor. A scan test controller coupled to the plurality of distributed slave counters to provide control signals to the plurality of distributed slave counters to perform an at-speed test of the processor.
摘要翻译：组合式高速扫描测试。一种处理器，包括多个分布式从属计数器。每个分布式从计数器耦合到一组扫描链，每个分布式从计数器产生要由耦合到每个分布式从计数器的扫描链组接收的移位使能触发器信号，至少移位使能触发信号部分地由处理器接收到的外部移位使能信号。耦合到所述多个分布式从属计数器的扫描测试控制器，以向多个分布式从计数器提供控制信号，以执行处理器的速度测试。

3. 发明申请

US20160092353A1 ESTABLISHING COLD STORAGE POOLS FROM AGING MEMORY 审中-公开
标题翻译：从老化记忆建立冷藏库
公开(公告)号：US20160092353A1
公开(公告)日：2016-03-31
申请号：US14496773
申请日：2014-09-25
申请人： Robert C. Swanson , Robert W. Cone , Brian R. Bennett , Vladimir Matveyenko , Paul D. Herring , Jordan A. Horwich , Tuan M. Quach , Cuong D. Dinh , Paul M. Leung , Luis E. Valdez , Joseph Hamann , Russell A. Hamann , Michael P. Pham , Caleb C. Molitoris , Kervin T. Ngo , Cory Li , Ola Fadiran , Jason R. Ng , Richard I. Guerin , Jay H. Danver , Chris Kun K. Cheung , Satish R. Natla , Rodel I. Cruz-Herrera
发明人： Robert C. Swanson , Robert W. Cone , Brian R. Bennett , Vladimir Matveyenko , Paul D. Herring , Jordan A. Horwich , Tuan M. Quach , Cuong D. Dinh , Paul M. Leung , Luis E. Valdez , Joseph Hamann , Russell A. Hamann , Michael P. Pham , Caleb C. Molitoris , Kervin T. Ngo , Cory Li , Ola Fadiran , Jason R. Ng , Richard I. Guerin , Jay H. Danver , Chris Kun K. Cheung , Satish R. Natla , Rodel I. Cruz-Herrera
IPC分类号： G06F12/06 , G06F12/12 , G06F11/30
CPC分类号： G11C29/765 , G06F11/3037 , G06F11/3055 , G06F12/0238 , G06F2201/88 , G06F2212/7202 , G06F2212/7203 , G06F2212/7206
摘要： Systems and methods may provide for detecting a pending write operation directed to a target memory region and determining whether the target memory region satisfies a degradation condition in response to the pending write operation. Additionally, the target memory region may be automatically reconfigured as a cold storage region if the target memory region satisfies the degradation condition. In one example, determining whether the target memory region satisfies the degradation condition includes updating the number of write operations directed to the target memory region based on the pending write operation and comparing the number of write operations to an offset value, wherein the degradation condition is satisfied if the number of write operations exceeds the offset value.
摘要翻译：系统和方法可以提供用于检测针对目标存储器区域的待决写入操作，并且确定目标存储器区域是否满足等待写入操作的退化条件。此外，如果目标存储器区域满足劣化条件，则可以将目标存储器区域自动重新配置为冷存储区域。在一个示例中，确定目标存储器区域是否满足劣化条件包括基于挂起的写入操作来更新针对目标存储器区域的写入操作的数量，并将写入操作的数量与偏移值进行比较，其中劣化条件是如果写操作的数量超过偏移值，则满足。

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