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1. 发明申请

US20060128112A1 Technique and methodology to passivate inductively coupled surface currents 有权
标题翻译：钝化电感耦合表面电流的技术和方法
公开(公告)号：US20060128112A1
公开(公告)日：2006-06-15
申请号：US11010970
申请日：2004-12-12
申请人： Sean Erickson , Jason Hudson
发明人： Sean Erickson , Jason Hudson
IPC分类号： H01L21/76
CPC分类号： H01L27/08 , H01L21/76224
摘要： A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively coupled surface currents to small areas that are then isolated from the rest of the chip.
摘要翻译：在电感线圈的区域下方形成深n阱。使用深n阱通过将二极管与层间电介质盖串联放置来减小寄生电容。深n阱也降低了基板噪声。一旦n阱被植入和退火，在n阱上形成浅沟槽隔离的交叉阴影线。浅沟槽隔离减小并将电感耦合表面电流限制在与芯片其余部分隔离的小区域上。

2. 发明申请

US20080064180A1 METHOD FOR PASSIVATING INDUCTIVELY COUPLED SURFACE CURRENTS IN A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中吸收感应耦合表面电流的方法
公开(公告)号：US20080064180A1
公开(公告)日：2008-03-13
申请号：US11856196
申请日：2007-09-17
申请人： SEAN ERICKSON , Jason Hudson
发明人： SEAN ERICKSON , Jason Hudson
IPC分类号： H01L21/76
CPC分类号： H01L27/08 , H01L21/76224
摘要： A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively coupled surface currents to small areas that are then isolated from the rest of the chip.
摘要翻译：在电感线圈的区域下方形成深n阱。使用深n阱通过将二极管与层间电介质盖串联放置来减小寄生电容。深n阱也降低了基板噪声。一旦n阱被植入和退火，在n阱上形成浅沟槽隔离的交叉阴影线。浅沟槽隔离减小并将电感耦合表面电流限制在与芯片其余部分隔离的小区域上。

3. 发明申请

US20060128113A1 Technique and methodology to passivate inductively or capacitively coupled surface currents under capacitor structures 有权
标题翻译：在电容器结构下钝化电感或电容耦合表面电流的技术和方法
公开(公告)号：US20060128113A1
公开(公告)日：2006-06-15
申请号：US11248509
申请日：2005-10-12
申请人： Sean Erickson , Jason Hudson
发明人： Sean Erickson , Jason Hudson
IPC分类号： H01L21/76
CPC分类号： H01L27/08 , H01L21/76224
摘要： A deep n-well is formed beneath the area of a capacitor structure. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively and/or capacitively coupled surface currents to small areas that are then isolated from the rest of the chip.
摘要翻译：在电容器结构的区域下方形成深n阱。使用深n阱通过将二极管与层间电介质盖串联放置来减小寄生电容。深n阱也降低了基板噪声。一旦n阱被植入和退火，在n阱上形成浅沟槽隔离的交叉阴影线。浅沟槽隔离减小并限制电感和/或电容耦合的表面电流到与芯片的其余部分隔离的小区域。

4. 发明申请

US20070096252A1 Multi-surfaced plate-to-plate capacitor and method of forming same 有权
标题翻译：多表面平板电容器及其形成方法
公开(公告)号：US20070096252A1
公开(公告)日：2007-05-03
申请号：US11266133
申请日：2005-11-02
申请人： Jason Hudson , Sean Erickson , Michael Saunders
发明人： Jason Hudson , Sean Erickson , Michael Saunders
IPC分类号： H01L29/00
CPC分类号： H01G4/33 , H01G4/228 , H01G4/38 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A plate to plate capacitor has a first plate, a second plate, and an insulating medium separating the first plate from the second plate. The first plate and the second plate are adapted and arranged to form an interlaced structure in which multiple capacitance surface areas in different planes, such as horizontal and vertical, are provided between said first and second plates. The plate to plate capacitor can be formed as a stack of layers in which one or more alternating first and third insulating layers each have first and second conductive lines configured therein and in which one or more second insulating layers having conductive vias formed therein interpose respective first and third insulating layers. The first and second conductive lines in the first insulating layer(s) are interconnected by the conductive vias to the first and second conductive lines, respectively, in the third layer(s) so as to interlace the first and second metal conductive lines together.
摘要翻译：平板电容器具有第一板，第二板和将第一板与第二板分离的绝缘介质。第一板和第二板被适配和布置成形成交错结构，其中在所述第一和第二板之间提供诸如水平和垂直的不同平面中的多个电容表面积。平板电容器可以形成为一叠层，其中一个或多个交替的第一和第三绝缘层各自具有配置在其中的第一和第二导电线，并且其中形成有导电通孔的一个或多个第二绝缘层插入相应的第一和第三绝缘层。第一绝缘层中的第一和第二导线分别通过导电通孔互连到第三层中的第一和第二导线，以将第一和第二金属导线交织在一起。

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