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    • 2. 发明申请
    • Systems and Methods for State Based Test Case Generation for Software Validation
    • 用于软件验证的基于状态的测试用例生成的系统和方法
    • US20140068339A1
    • 2014-03-06
    • US13599351
    • 2012-08-30
    • Jared M. Farnsworth
    • Jared M. Farnsworth
    • G06F11/22
    • G06F11/3684
    • Systems and methods for state based test case generation for software validation are disclosed. One embodiment includes determining a first input and a first input type for a program block of vehicle software for creating a test case, wherein the first input type includes a state based input, determining permutations of values for the first input, based on the first input type, and running the test case with the state based input, wherein running the test case comprises applying the permutations of values for the first input to the program block. Some embodiments include determining, by a test computing device, whether the test case meets a predetermined level of modified condition/decision coverage (MC/DC) and providing an indication of whether the test case meets the predetermined level of MC/DC.
    • 披露了基于状态的测试用例生成软件验证的系统和方法。 一个实施例包括确定用于创建测试用例的车辆软件的程序块的第一输入和第一输入类型,其中所述第一输入类型包括基于状态的输入,基于所述第一输入来确定所述第一输入的值的排列 类型,并使用基于状态的输入运行测试用例,其中运行测试用例包括将第一输入的值的排列应用于程序块。 一些实施例包括由测试计算设备确定测试用例是否满足修改的条件/判定覆盖(MC / DC)的预定级别,并提供测试用例是否满足预定级别的MC / DC的指示。
    • 4. 发明申请
    • Multiple ECU Software-In-The-Loop Simulation Environment
    • 多个ECU软件 - 环路仿真环境
    • US20100333070A1
    • 2010-12-30
    • US12492710
    • 2009-06-26
    • Jared M. Farnsworth
    • Jared M. Farnsworth
    • G06F9/44G06F12/00G06F12/02
    • G06F11/3457
    • The invention relates to methods for evaluating the performance of a system having a plurality of electronic control unit (ECU) software programs. A plurality of first memory spaces are allocated for use by the software programs. At least one second memory space is allocated to be in communication with these first memory spaces. The output of at least one first software program is stored in at least one of said first memory spaces associated with that program, wherein said output is subsequently transmitted to at least one said second memory space, and wherein said output is further subsequently transmitted to at least one of said first memory spaces associated with at least one second software program. From this location, said output is accessed as an input for said second software program. The performance of the system is evaluated by executing said software programs and determining if the outputs of said programs satisfy the criteria of the system.
    • 本发明涉及用于评估具有多个电子控制单元(ECU)软件程序的系统的性能的方法。 多个第一存储器空间被分配供软件程序使用。 至少一个第二存储器空间被分配为与这些第一存储器空间通信。 至少一个第一软件程序的输出被存储在与该程序相关联的所述第一存储器空间中的至少一个中,其中所述输出随后被发送到至少一个所述第二存储器空间,并且其中所述输出进一步随后被发送到 与至少一个第二软件程序相关联的所述第一存储空间中的至少一个。 从该位置,所述输出作为所述第二软件程序的输入被访问。 通过执行所述软件程序并确定所述程序的输出是否满足系统的标准来评估系统的性能。
    • 6. 发明授权
    • Method for validation of a graphically based executable control specification using model extraction
    • 使用模型提取验证基于图形的可执行控制规范的方法
    • US08751094B2
    • 2014-06-10
    • US13714255
    • 2012-12-13
    • Jared M. FarnsworthKoichi UedaHakan Yazarel
    • Jared M. FarnsworthKoichi UedaHakan Yazarel
    • G06F7/00
    • G06F8/20G05B19/0426G05B2219/24034
    • A system and method to hierarchically validate graphically based executable logic control specifications. The method may include performing an open loop validation of a feature of a plurality of features in the control specification, performing an open loop validation of the functional hierarchy of an application of a plurality of applications in the graphically based logic control specification in response to completing successful validation of the plurality of features, performing a closed loop validation an ECU model of a plurality of ECUs modeled in the graphically based logic control specification in response to completing successful validation of the plurality of applications, and performing a closed loop validation of the plurality of ECUs modeled in response to completing successful validation of the ECU modeled.
    • 一种用于分层验证基于图形的可执行逻辑控制规范的系统和方法。 该方法可以包括执行控制规范中的多个特征的特征的开环验证,响应于完成,在基于图形的逻辑控制规范中对多个应用的​​应用的功能层次进行开环验证 成功地验证多个特征,响应于完成多个应用程序的成功验证,执行在图形逻辑控制规范中建模的多个ECU的ECU模型的闭环验证,以及执行多个特征的闭环验证 的ECU模拟响应完成成功验证的ECU模型。
    • 7. 发明授权
    • Hierarchical accumulated validation system and method
    • 分层累积验证系统和方法
    • US08751093B2
    • 2014-06-10
    • US13448304
    • 2012-04-16
    • Jared M. FarnsworthKoichi UedaHakan Yazarel
    • Jared M. FarnsworthKoichi UedaHakan Yazarel
    • G06F7/00
    • B60W50/04B60W2050/0006
    • The present disclosure generally relates to improvements in validating control specifications and more particularly pertains to a system and method to hierarchically validate graphically based executable logic control specifications. This method may include identifying, by a processor for hierarchically validating a graphically based logic control specification, a functional hierarchy of a first application of the control specification comprising a first feature. The method may include executing, by the processor, a specific first feature test case on the first feature to at least one of validate a structure of the first feature and validate that a specific functional requirement of the first feature is met.
    • 本公开通常涉及对验证控制规范的改进,更具体地涉及用于分层验证基于图形的可执行逻辑控制规范的系统和方法。 该方法可以包括由处理器识别用于分层验证基于图形的逻辑控制规范,包括第一特征的控制规范的第一应用的功能层级。 该方法可以包括由处理器执行第一特征上的特定第一特征测试用例以验证第一特征的结构并验证第一特征的特定功能需求是否被满足中的至少一个。