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1. 发明授权

US08024698B2 ASICs having more features than generally usable at one time and methods of use 有权
公开(公告)号：US08024698B2
公开(公告)日：2011-09-20
申请号：US11829450
申请日：2007-07-27
申请人： James T. Koo
发明人： James T. Koo
IPC分类号： G06F17/50
摘要： More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different market development probabilities in a host of different market spaces and a subset of the excessive ASIC functionality is programmably activated in each market space after manufacture. In one embodiment, a mega-ASIC with excessive ASIC functionality crammed into it, has a universal core as well as plurality of programmably selectable ASIC function blocks. The ASIC function blocks are programmably activatable and de-activatable so that a mass produced can quickly respond to shifting market demands.

2. 发明授权

US07251805B2 ASICs having more features than generally usable at one time and methods of use 有权
标题翻译：具有比一般可用的特征和使用方法更多的特征的ASIC
公开(公告)号：US07251805B2
公开(公告)日：2007-07-31
申请号：US10964456
申请日：2004-10-12
申请人： James T. Koo
发明人： James T. Koo
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different market development probabilities in a host of different market spaces and a subset of the excessive ASIC functionality is programmably activated in each market space after manufacture. In one embodiment, a mega-ASIC with excessive ASIC functionality crammed into it, has a universal core as well as plurality of programmably selectable ASIC function blocks. The ASIC function blocks are programmably activatable and de-activatable so that a mass produced can quickly respond to shifting market demands.
摘要翻译：当芯片被封装并插入到更广泛的电路中时，更多的ASIC功能被封装到芯片（或芯片组）中，可能或绝对可操作。选择过多的ASIC功能以应对不同市场空间的不同的市场开发概率，并且在制造之后的每个市场空间中可编程地激活过多的ASIC功能的一部分。在一个实施例中，具有过多的ASIC功能的大型ASIC被挤入其中，具有通用核心以及多个可编程选择的ASIC功能块。 ASIC功能块可编程激活和不可激活，使得生产的质量可以快速响应市场需求的变化。

3. 发明授权

US4837748A Counting RAM 失效
标题翻译：计数RAM
公开(公告)号：US4837748A
公开(公告)日：1989-06-06
申请号：US38107
申请日：1987-04-14
申请人： Shine C. Chung , Siu K. Tsang , James T. Koo , Sho Long S. Chen , John Y. Chan
发明人： Shine C. Chung , Siu K. Tsang , James T. Koo , Sho Long S. Chen , John Y. Chan
IPC分类号： G11C8/00 , G11C8/04 , G11C16/10
CPC分类号： G11C8/00 , G11C16/102 , G11C8/04
摘要： An integrated circuit memory with additional circuitry added so that the integrated circuit acts as a counting memory is disclosed. A memory core is included with associated circuitry allowing it to be accessed in the same manner as ordinary random access memory (RAM). A counter is included and is coupled so that it can receive the contents of any location in the memory core. Each address in the memory acts as an individual counter. When a particular memory address is presented indicating that the count at that memory location should be incremented, the contents of that memory location are transferred to the counter, the counter is incremented, and the contents of the counter are then transferred back to the memory location. This process is repeated each time a new address is presented indicating a new event to be recorded. At the end of a series of events, the core memory will contain, at each corresponding memory location, the number of occurrences of the event assigned to that address.
摘要翻译：公开了一种具有附加电路的集成电路存储器，其中集成电路充当计数存储器。存储器核心包括在相关联的电路中，允许以与普通随机存取存储器（RAM）相同的方式访问存储器核心。计数器被包括并被耦合，使得它可以接收存储器核心中的任何位置的内容。内存中的每个地址都充当个别计数器。当呈现特定存储器地址指示该存储器位置处的计数应当递增时，该存储器位置的内容被传送到计数器，计数器递增，并且计数器的内容然后被传送回存储器位置。每当呈现指示要记录的新事件的新地址时，重复此过程。在一系列事件结束时，核心内存将在每个对应的内存位置包含分配给该地址的事件的发生次数。

4. 发明授权

US4012757A Contactless random-access memory cell and cell pair 失效
标题翻译：非接触式随机存取存储器单元和单元对
公开(公告)号：US4012757A
公开(公告)日：1977-03-15
申请号：US575034
申请日：1975-05-05
申请人： James T. Koo
发明人： James T. Koo
IPC分类号： G11C11/35 , G11C11/404 , H01L21/8242 , H01L27/07 , H01L27/10 , H01L27/108
CPC分类号： H01L27/0733 , G11C11/35 , G11C11/404 , H01L27/10805
摘要： A one device per bit random access memory cell and array is constructed with integrated circuit MOSFET transistors as the memory cell switching elements. Information transfer is accomplished by transferring incremental charges between a capacitor to a sense bit line. The capacitor is comprised of a region disposed in the substrate and a constantly charged polycrystalline plate insulatively disposed above the semiconductor substrate. The MOSFETS have a merged sense line and source region and have omitted a separate diffusion for their drain region by merging the drain with the capacitor region. The storage devices are grouped in pairs and share a common gate member and a common capacitive plate. Therefore, a single contact window is provided to the common gate member and the use of one half of the minimum contact area is allocated per device. By means of an interdigitated topology, a memory cell pair is devised having a small field area with a relatively large cell to bit line capacitance ratio.
摘要翻译：每一位器件每位随机存取存储单元和阵列由集成电路MOSFET晶体管构成，作为存储单元开关元件。通过在电容器到感测位线之间传递增量电荷来实现信息传输。电容器由设置在基板中的区域和绝缘地设置在半导体基板上方的恒定带电的多晶板构成。 MOSFETs具有合并的感测线和源极区域，并且通过将漏极与电容器区域合并而省略了漏极区域的单独扩散。存储设备成对分组，并共享公共门构件和公共电容板。因此，向公共门构件提供单个接触窗口，并且每个设备分配使用最小接触面积的一半。通过叉指拓扑，设计出具有相对大的单元到位线电容比的小场区的存储单元对。

5. 发明授权

US08341581B2 ASICs having programmable bypass of design faults 有权
标题翻译：具有设计故障可编程旁路的ASIC
公开(公告)号：US08341581B2
公开(公告)日：2012-12-25
申请号：US12145275
申请日：2008-06-24
申请人： James T. Koo
发明人： James T. Koo
IPC分类号： G06F17/50
CPC分类号： G06F21/76 , G01R31/3177 , G06F11/0706 , G06F11/0751 , G06F11/079 , G06F11/0793 , G06F11/20
摘要： A relatively small amount of programmable or reprogrammable logic (pro-Logic) is included in a mostly-ASIC device so that such re/programmable logic can be used as a substitute for, or for bypassing a fault-infected ASIC block (if any) either permanently or at times when the fault-infected ASIC block is about to perform a fault-infected operation (bug-infected operation): The substitution or bypass does not have to be a permanent one that is in effect at all times for the entirety of the fault-infected ASIC block. Instead affected outputs of the faulty ASIC block can be disabled from working just at the time they would otherwise initiate or propagate an error. Such fault-infected operations of the temporarily deactivated ASIC block(s) may be substituted for by appropriately programmed pro-Logic at the appropriate times.
摘要翻译：大多数ASIC设备中包含相对少量的可编程或可重新编程的逻辑（pro-Logic），以便这样的可重新编程逻辑可以用作替代或绕过故障感染的ASIC块（如果有的话）永久或有时候，受到故障的ASIC块即将执行故障感染操作（错误感染的操作）：替代或旁路不一定是永久性的，在整个过程中始终有效的故障感染ASIC块。故障ASIC块的相反影响的输出可以在其他情况下启动或传播错误时被禁止工作。临时停用的ASIC块的这种故障感染操作可以在适当的时间被适当编程的pro-Logic代替。

6. 发明申请

US20120096415A1 ASICS HAVING MORE FEATURES THAN GENERALLY USABLE AT ONE TIME AND METHODS OF USE 有权
标题翻译： ASICS具有一般可用的更多功能和使用方法
公开(公告)号：US20120096415A1
公开(公告)日：2012-04-19
申请号：US13236398
申请日：2011-09-19
申请人： James T. Koo
发明人： James T. Koo
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A present ASIC may include functionality exceeding that which will be operative at one given time (e.g., when the chip is packaged and inserted into a broader circuit. The excess ASIC functionality may be chosen in anticipation of changing market environments, and/or differing product requirements in various market spaces (e.g., in different countries where different interoperability standards are chosen). In such cases, and an appropriate subset of the excessive ASIC functionality may be programmably activated for each market space after manufacture.
摘要翻译：目前的ASIC可以包括超过在一个给定时间可操作的功能（例如，当芯片被封装并插入到更广泛的电路中时），可以选择多余的ASIC功能来预期变化的市场环境和/或不同的产品在各种市场空间（例如，选择不同互操作性标准的不同国家）的需求，在这种情况下，过多的ASIC功能的适当子集可以在制造后的每个市场空间可编程地激活。

7. 发明授权

US08136083B2 ASICs having more features than generally usable at one time and methods of use 有权
标题翻译：具有比一般可用的特征和使用方法更多的特征的ASIC
公开(公告)号：US08136083B2
公开(公告)日：2012-03-13
申请号：US11829450
申请日：2007-07-27
申请人： James T. Koo
发明人： James T. Koo
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different market development probabilities in a host of different market spaces and a subset of the excessive ASIC functionality is programmably activated in each market space after manufacture. In one embodiment, a mega-ASIC with excessive ASIC functionality crammed into it, has a universal core as well as plurality of programmably selectable ASIC function blocks. The ASIC function blocks are programmably activatable and de-activatable so that a mass produced can quickly respond to shifting market demands.
摘要翻译：当芯片被封装并插入到更广泛的电路中时，更多的ASIC功能被封装到芯片（或芯片组）中，可能或绝对可操作。选择过多的ASIC功能以应对不同市场空间的不同的市场开发概率，并且在制造之后的每个市场空间中可编程地激活过多的ASIC功能的一部分。在一个实施例中，具有过多的ASIC功能的大型ASIC被挤入其中，具有通用核心以及多个可编程选择的ASIC功能块。 ASIC功能块可编程激活和不可激活，使得生产的质量可以快速响应市场需求的变化。

8. 发明授权

US4048518A MOS buffer circuit 失效
标题翻译： MOS缓冲电路
公开(公告)号：US4048518A
公开(公告)日：1977-09-13
申请号：US754119
申请日：1976-12-27
申请人： James T. Koo
发明人： James T. Koo
IPC分类号： H03K19/0185 , H03K19/40 , H03K17/04
CPC分类号： H03K19/018507
摘要： An MOS buffer circuit particularly suitable as an input stage for receiving a lower level input signal in an MOS integrated circuit. A transistor is employed to decouple an input transistor from a load, thereby allowing an output signal from the circuit to rise more quickly.
摘要翻译：特别适用于在MOS集成电路中接收较低电平输入信号的输入级的MOS缓冲电路。使用晶体管将输入晶体管与负载去耦，从而允许来自电路的输出信号更快地上升。

9. 发明授权

US3978459A High density MOS memory array 失效
标题翻译：高密度MOS存储器阵列
公开(公告)号：US3978459A
公开(公告)日：1976-08-31
申请号：US569927
申请日：1975-04-21
申请人： James T. Koo
发明人： James T. Koo
IPC分类号： G11C11/4091 , H03K3/356 , G11C11/40
CPC分类号： H03K3/356052 , G11C11/4091 , H03K3/356095
摘要： A high density MOS integrated circuit memory array utilizing single device dynamic cells and a uniquely controlled sense amplifier. The loads of the sense amplifier are also used to precharge bit lines thereby reducing the number of devices used in prior art arrays. A single noise suppression circuit provides planar noise suppression, the circuit is clocked with the same signals used to control the sense amplifier.

10. 发明申请

US20100026339A1 ASICs Having More Features Than Generally Usable At One Time and Methods of Use 有权
标题翻译：具有比一般可用的更多功能的ASIC和使用方法
公开(公告)号：US20100026339A1
公开(公告)日：2010-02-04
申请号：US11829450
申请日：2007-07-27
申请人： James T. KOO
发明人： James T. KOO
IPC分类号： H03K19/02
CPC分类号： G06F17/5045
摘要： More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different market development probabilities in a host of different market spaces and a subset of the excessive ASIC functionality is programmably activated in each market space after manufacture. In one embodiment, a mega-ASIC with excessive ASIC functionality crammed into it, has a universal core as well as plurality of programmably selectable ASIC function blocks. The ASIC function blocks are programmably activatable and de-activatable so that a mass produced can quickly respond to shifting market demands.
摘要翻译：当芯片被封装并插入到更广泛的电路中时，更多的ASIC功能被封装到芯片（或芯片组）中，可能或绝对可操作。选择过多的ASIC功能以应对不同市场空间的不同的市场开发概率，并且在制造之后的每个市场空间中可编程地激活过多的ASIC功能的一部分。在一个实施例中，具有过多的ASIC功能的大型ASIC被挤入其中，具有通用核心以及多个可编程选择的ASIC功能块。 ASIC功能块可编程激活和不可激活，使得生产的质量可以快速响应市场需求的变化。

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