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1. 发明授权

US5379193A Parallel processor structure and package 失效
标题翻译：并行处理器结构和封装
公开(公告)号：US5379193A
公开(公告)日：1995-01-03
申请号：US97520
申请日：1993-07-27
申请人： Thomas P. Gall , James R. Loomis
发明人： Thomas P. Gall , James R. Loomis
IPC分类号： G06F1/18 , G06F15/173 , G06F15/80 , G11C5/00 , H01L21/822 , H01L23/52 , H01L27/04 , H05K1/03 , H05K3/00 , H05K3/46 , H05K1/14
CPC分类号： H05K3/4691 , H05K1/0373 , H05K2201/015 , H05K2201/09109 , H05K2201/10159 , H05K3/4641
摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate.
摘要翻译：公开了一种并行处理器封装结构和用于制造该结构的方法。单独的逻辑和存储器元件在印刷电路卡上。这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。通过在层压板中实现的开关结构来提供互通。印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信，轴向电路（通孔和通孔）。

2. 发明授权

US5403420A Fabrication tool and method for parallel processor structure and package 失效
标题翻译：并行处理器结构和封装的制作工具和方法
公开(公告)号：US5403420A
公开(公告)日：1995-04-04
申请号：US97603
申请日：1993-07-27
申请人： Thomas P. Gall , James R. Loomis , David B. Stone , Cheryl L. Tytran , James Wilcox
发明人： Thomas P. Gall , James R. Loomis , David B. Stone , Cheryl L. Tytran , James Wilcox
IPC分类号： G11C5/00 , H05K3/00 , H05K3/46 , B32B31/00
CPC分类号： H05K3/462 , B32B37/1207 , B32B2327/12 , B32B2379/00 , B32B2457/00 , H05K2201/015 , H05K2201/0154 , H05K2201/09536 , H05K2203/068 , H05K3/4623 , H05K3/4641 , H05K3/4691 , Y10T29/49105
摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate.
摘要翻译：公开了一种并行处理器封装结构和用于制造该结构的方法。单独的逻辑和存储器元件在印刷电路卡上。这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。通过在层压板中实现的开关结构来提供互通。印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信，轴向电路（通孔和通孔）。

3. 发明授权

US4969979A Direct electroplating of through holes 失效
标题翻译：直通电镀通孔
公开(公告)号：US4969979A
公开(公告)日：1990-11-13
申请号：US348844
申请日：1989-05-08
申请人： Bernd K. Appelt , Perminder Bindra , Robert D. Edwards , James R. Loomis , Jae M. Park , Jonathan D. Reid , Lisa J. Smith , James R. White
发明人： Bernd K. Appelt , Perminder Bindra , Robert D. Edwards , James R. Loomis , Jae M. Park , Jonathan D. Reid , Lisa J. Smith , James R. White
IPC分类号： C25D5/56 , H05K3/42
CPC分类号： C25D5/56 , H05K3/424 , H05K2203/0716 , H05K2203/122 , H05K3/427
摘要： Substantially nonconductive or semiconductive surfaces of through holes can be electroplated directly, without an intervening non-electrolytic metallization, by a stepwise process which includes the application to the through holes of a polyelectrolyte surfactant in solution in combination with the application of a conductive metal containing material.

4. 发明授权

US4960634A Epoxy composition of increased thermal conductivity and use thereof 失效
标题翻译：增加导热性的环氧组合物及其用途
公开(公告)号：US4960634A
公开(公告)日：1990-10-02
申请号：US494807
申请日：1990-03-14
申请人： Christina M. Boyko , Craig N. Johnston , James R. Loomis , Carl E. Samuelson , Ricahrd A. Schumacher
发明人： Christina M. Boyko , Craig N. Johnston , James R. Loomis , Carl E. Samuelson , Ricahrd A. Schumacher
IPC分类号： C08G59/30 , C08G59/38 , H05K1/02 , H05K1/03
CPC分类号： H05K1/0373 , C08G59/30 , C08G59/38 , H05K1/0203 , H05K2201/0209 , H05K2203/125 , Y10T428/24917
摘要： A composition of enhanced thermal conductivity which comprises a tetrabrominated diglycidyl ether polyepoxide; and epoxy polymer having an epoxy functionality of 3.5 to 6; zinc oxide and curing agents; and use thereof.
摘要翻译：包含四溴化二缩水甘油醚聚环氧化物的增强导热性组合物; 环氧官能度为3.5〜6的环氧聚合物; 氧化锌和固化剂; 及其用途。

5. 发明授权

US5280414A Au-Sn transient liquid bonding in high performance laminates 失效
标题翻译： Au-Sn瞬态液体粘合在高性能层压板中
公开(公告)号：US5280414A
公开(公告)日：1994-01-18
申请号：US536145
申请日：1990-06-11
申请人： Charles R. Davis , Richard Hsiao , James R. Loomis , Jae M. Park , Jonathan D. Reid
发明人： Charles R. Davis , Richard Hsiao , James R. Loomis , Jae M. Park , Jonathan D. Reid
IPC分类号： H01R43/02 , B23K35/00 , B23K35/30 , H01R4/02 , H05K3/28 , H05K3/32 , H05K3/40 , H05K3/46 , H05K3/36 , B32B31/00 , H05K1/11
CPC分类号： B23K35/3013 , B23K35/001 , H01R4/02 , H05K3/4614 , H01L2924/0132 , H05K2201/0305 , H05K3/28 , H05K3/328 , H05K3/4038 , Y10S428/901 , Y10T156/1056 , Y10T29/49126
摘要： A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au-Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, multilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.
摘要翻译：公开了一种同时层压电路化电介质层以形成多层高性能电路板并制造层间电连接的方法。该方法选择将在一个低温下形成共晶体的两种元素，并且将固化形成合金，该合金将仅在任何后续层压所需的第二温度下再熔化。使用瞬态液体粘合技术和足够的Au和Sn制成接头，以在低温下产生Au-Sn20wt％共晶。一旦固化，形成的合金在随后的叠片中保持固体。结果，制造复合多层高性能电路板，通过固体合金在选定的焊盘处电连接。

6. 发明授权

US5421507A Au-Sn transient liquid bonding in high performance laminates 失效
标题翻译： Au-Sn瞬态液体粘合在高性能层压板中
公开(公告)号：US5421507A
公开(公告)日：1995-06-06
申请号：US134994
申请日：1993-10-12
申请人： Charles R. Davis , Richard Hsiao , James R. Loomis , Jae M. Park , Jonathan D. Reid
发明人： Charles R. Davis , Richard Hsiao , James R. Loomis , Jae M. Park , Jonathan D. Reid
IPC分类号： H01R43/02 , B23K35/00 , B23K35/30 , H01R4/02 , H05K3/28 , H05K3/32 , H05K3/40 , H05K3/46 , B23K1/00
CPC分类号： B23K35/3013 , B23K35/001 , H01R4/02 , H05K3/4614 , H01L2924/0132 , H05K2201/0305 , H05K3/28 , H05K3/328 , H05K3/4038 , Y10S428/901 , Y10T156/1056 , Y10T29/49126
摘要： A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au--Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, mulilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.
摘要翻译：公开了一种同时层压电路化电介质层以形成多层高性能电路板并制造层间电连接的方法。该方法选择将在一个低温下形成共晶体的两种元素，并将固化形成合金，该合金将仅在任何后续层压所要求的第二温度下再熔化。使用瞬态液体粘合技术和足够的Au和Sn制成接头，以在低温下产生Au-Sn20wt％共晶。一旦固化，形成的合金在随后的叠片中保持固体。结果，制造复合的，多层的高性能电路板，通过固体合金在选定的焊盘处电连接。

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