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1. 发明授权

US08032713B2 Structure for handling data access 失效
标题翻译：用于处理数据访问的结构
公开(公告)号：US08032713B2
公开(公告)日：2011-10-04
申请号：US12115146
申请日：2008-05-05
申请人： James J. Allen, Jr. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
发明人： James J. Allen, Jr. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to the storage device that can be speculatively issued, and circuitry for intermixing demand accesses and speculative accesses in accordance with the speculative access threshold.
摘要翻译：提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。该设计结构通常包括计算机系统，其包括CPU，存储设备，用于提供与可推测发布的对存储设备的访问总数的所选百分比相对应的推测访问阈值的电路，以及用于混合需求的电路根据投机访问阈值访问和推测访问。

2. 发明授权

US08028257B2 Structure for data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode 有权
标题翻译：在可变延迟模式下工作的FBDIMM存储器系统中数据总线带宽调度的结构
公开(公告)号：US08028257B2
公开(公告)日：2011-09-27
申请号：US12110765
申请日：2008-04-28
申请人： James J. Allen, Jr. , Steven K. Jenkins , Michael R. Trombley
发明人： James J. Allen, Jr. , Steven K. Jenkins , Michael R. Trombley
IPC分类号： G06F17/50 , G06F12/06 , G06F13/00
CPC分类号： G06F13/1689
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system is provided. A scheduling algorithm pre-computes return time data for data connected to DRAM buffer chips and stores the return time data in a table. The return time data is expressed as data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.
摘要翻译：提供了一种体现在机器可读存储介质中的设计结构，用于在FBDIMM存储器子系统中使用可变延迟模式来设计，制造和/或测试用于调度数据请求的服务的设计。调度算法预先计算连接到DRAM缓冲器芯片的数据的返回时间数据，并将返回时间数据存储在表中。返回时间数据表示为在每个向量中一位等于“1”的数据返回时间二进制向量。对于每个接收到的数据请求，存储器控制器检索适当的返回时间向量。此外，调度算法利用更新的历史向量来确定接收到的请求是否对执行请求产生冲突。通过计算和利用每个请求的分数，调度算法重新排序和调度所选择的请求的执行，以尽可能地保留尽可能多的数据总线带宽，同时避免冲突。

3. 发明授权

US08019049B2 Method for generating reliability tests based on orthogonal arrays and field data 有权
标题翻译：基于正交阵列和现场数据生成可靠性测试的方法
公开(公告)号：US08019049B2
公开(公告)日：2011-09-13
申请号：US11691665
申请日：2007-03-27
申请人： James J. Allen, Jr. , Janet Kenny , John Yeager , Muharrem Umit Uyar , Linda Yeager
发明人： James J. Allen, Jr. , Janet Kenny , John Yeager , Muharrem Umit Uyar , Linda Yeager
IPC分类号： H04M1/24 , H04M3/08 , H04M3/22
CPC分类号： H04M3/28
摘要： A method for generating reliability tests for a telephone system is based upon sampling an orthogonal array which covers various combinations of test parameters. Field data is collected of actual telephone activity on a telephone system. The field data is evaluated so as to determine call-mix characteristics. Probabilistic weights for the different call-mix characteristics are obtained, and then the probabilistic weights are used to sample the test case scenarios generated in the orthogonal array which have the same call-mix characteristics. These test case scenarios are used to run tests on the telephone system. These tests are preferably performed using automated test scripts. After the test data is collected, reliability metrics are calculated from the test data.
摘要翻译：用于产生电话系统的可靠性测试的方法是基于对覆盖测试参数的各种组合的正交阵列的采样进行的。在电话系统上收集实际电话活动的现场数据。对现场数据进行评估，以确定呼叫混合特性。获得不同呼叫混合特性的概率权重，然后使用概率权重来对具有相同呼叫混合特性的正交阵列中生成的测试用例场景进行采样。这些测试用例场景用于在电话系统上运行测试。这些测试优选使用自动测试脚本进行。收集测试数据后，从测试数据计算可靠性度量。

4. 发明申请

US20090276559A1 Arrangements for Operating In-Line Memory Module Configurations 审中-公开
标题翻译：操作串行内存模块配置的安排
公开(公告)号：US20090276559A1
公开(公告)日：2009-11-05
申请号：US12114533
申请日：2008-05-02
申请人： James J. Allen, JR. , Robert J. Reese , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： James J. Allen, JR. , Robert J. Reese , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G06F12/06
CPC分类号： G06F13/1684 , G06F13/161
摘要： In one embodiment, a method is disclosed for timing responses to a plurality of memory requests. The method can include sending a plurality of memory requests to a plurality of in-line memory modules. The requests can be sent over a channel from a plurality of channels, where each channel can have a plurality of lanes. The method can receive responses to the plurality of memory requests over the channel and monitor the response to detect a timing relationship between at least two lanes from the plurality of lanes. In addition, the method can adjust a timing of a register loading and unloading sequence in response to the monitoring of multiple lanes and channels. Other embodiments are also disclosed.
摘要翻译：在一个实施例中，公开了一种用于对多个存储器请求进行定时响应的方法。该方法可以包括向多个在线存储器模块发送多个存储器请求。可以通过信道从多个信道发送请求，其中每个信道可以具有多个通道。该方法可以通过信道接收对多个存储器请求的响应，并监视响应以检测来自多个车道的至少两个车道之间的定时关系。此外，该方法可以响应于多个通道和通道的监视来调整寄存器加载和卸载序列的定时。还公开了其他实施例。

5. 发明申请

US20090003534A1 Telephone Software Testing System and Method 有权
标题翻译：电话软件测试系统和方法
公开(公告)号：US20090003534A1
公开(公告)日：2009-01-01
申请号：US11769472
申请日：2007-06-27
申请人： James J. Allen, JR. , Muharrem Umit Uyar , Michael Robert Lundberg , Diane Somers , Shashank Sarwate , William Howard Chriss
发明人： James J. Allen, JR. , Muharrem Umit Uyar , Michael Robert Lundberg , Diane Somers , Shashank Sarwate , William Howard Chriss
IPC分类号： H04M3/22
CPC分类号： H04M3/22 , H04M3/08 , H04M2203/1016
摘要： The present invention provides a system and method for a computer controlled test system in which the computer can change and monitor the compound observable state of an electronic device or telephone during testing procedure. In the preferred embodiment of the invention, the compound observable state of the electronic device includes a display bit map file or the status of lights or buttons. The compound observable state can be evaluated by the computer in real-time to alert nearby operators of a failure (i.e. a telephone that needs to be rebooted) or malfunction (not rising to the level of a failure). Also, the data related to the compound observable state can be stored in the computer for later review to assist in debugging the telephone's software.
摘要翻译：本发明提供了一种用于计算机控制测试系统的系统和方法，其中计算机可以在测试过程期间改变和监视电子设备或电话的复合可观察状态。在本发明的优选实施例中，电子设备的化合物可观察状态包括显示位图文件或灯或按钮的状态。可以由计算机实时评估复合可观察状态，以向附近的操作员警告故障（即，需要重新启动的电话）或故障（不升到故障水平）。此外，与复合可观察状态相关的数据可以存储在计算机中以便稍后复查以帮助调试电话的软件。

6. 发明申请

US20090150572A1 STRUCTURE FOR HANDLING DATA REQUESTS 失效
标题翻译：处理数据请求的结构
公开(公告)号：US20090150572A1
公开(公告)日：2009-06-11
申请号：US12114792
申请日：2008-05-04
申请人： JAMES J. ALLEN, JR. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
发明人： JAMES J. ALLEN, JR. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
IPC分类号： G06F3/00 , G06F5/12
CPC分类号： G06F12/0815 , G06F2212/507
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.
摘要翻译：提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。该设计结构通常包括计算机系统，其包括CPU，存储器控制器，存储器，连接CPU，存储器控制器和存储器的总线，用于提供与可读取总数的所选百分比相对应的推测读取阈值的电路推测性发布，以及根据推测读取阈值混合需求读取和推测读取的电路。

7. 发明授权

US07937533B2 Structure for handling data requests 失效
标题翻译：处理数据请求的结构
公开(公告)号：US07937533B2
公开(公告)日：2011-05-03
申请号：US12114792
申请日：2008-05-04
申请人： James J. Allen, Jr. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
发明人： James J. Allen, Jr. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0815 , G06F2212/507
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.
摘要翻译：提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。该设计结构通常包括计算机系统，其包括CPU，存储器控制器，存储器，连接CPU，存储器控制器和存储器的总线，用于提供与可读取总数的所选百分比相对应的推测读取阈值的电路推测性发布，以及根据推测读取阈值混合需求读取和推测读取的电路。

8. 发明授权

US07660952B2 Data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode 失效
标题翻译：在可变延迟模式下工作的FBDIMM存储系统中的数据总线带宽调度
公开(公告)号：US07660952B2
公开(公告)日：2010-02-09
申请号：US11680695
申请日：2007-03-01
申请人： James J. Allen, Jr. , Steven K. Jenkins , Michael R. Trombley
发明人： James J. Allen, Jr. , Steven K. Jenkins , Michael R. Trombley
IPC分类号： G06F12/06
CPC分类号： G06F13/4243
摘要： A method and system for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system. A scheduling algorithm pre-computes return time data for data connected to all DRAM buffer chips and stores the return time data in a table. The return time data is expressed as a set of data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector representing a compilation of data return time vectors of all executing requests to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.
摘要翻译：一种用于在FBDIMM存储器子系统中使用可变等待时间模式来调度数据请求的服务的方法和系统。调度算法预先计算连接到所有DRAM缓冲器芯片的数据的返回时间数据，并将返回时间数据存储在表中。返回时间数据表示为在每个向量中一位等于“1”的一组数据返回时间二进制向量。对于每个接收到的数据请求，存储器控制器检索适当的返回时间向量。此外，调度算法利用表示所有执行请求的数据返回时间向量的汇编的更新历史向量，以确定接收到的请求是否对执行请求产生冲突。通过计算和利用每个请求的分数，调度算法重新排序和调度所选择的请求的执行，以尽可能地保留尽可能多的数据总线带宽，同时避免冲突。

9. 发明授权

US07657771B2 Method and apparatus for reducing latency associated with read operations in a memory system 失效
标题翻译：用于减少与存储器系统中的读取操作相关联的延迟的方法和装置
公开(公告)号：US07657771B2
公开(公告)日：2010-02-02
申请号：US11621201
申请日：2007-01-09
申请人： James J. Allen, Jr. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
发明人： James J. Allen, Jr. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
IPC分类号： G06F1/04 , G06F13/00
CPC分类号： G06F13/1689
摘要： Methods and system for reducing latency associated with a read operation in a processor memory system are provided. In one implementation, the method includes receiving an early indicator corresponding to read data from a memory, delaying the early indicator in accordance with a pre-determined delay such that the early read indicator is passed to a bus in advance of the read data; and dynamically adjusting the pre-determined delay using an adjustment delay circuit, the pre-determined delay being adjusted responsive to a change in operational speed of the bus or change in operational speed of a processor coupled to the bus.
摘要翻译：提供了用于减少与处理器存储器系统中的读取操作相关联的延迟的方法和系统。在一个实现中，该方法包括从存储器接收对应于读取数据的早期指示符，根据预定延迟延迟早期指示符，使得早期读取指示符在读取数据之前被传递到总线; 以及使用调整延迟电路动态调整预定延迟，响应于总线的操作速度的变化或耦合到总线的处理器的操作速度的改变来调整预定的延迟。

10. 发明申请

US20090150618A1 STRUCTURE FOR HANDLING DATA ACCESS 失效
标题翻译：处理数据访问的结构
公开(公告)号：US20090150618A1
公开(公告)日：2009-06-11
申请号：US12115146
申请日：2008-05-05
申请人： James J. Allen, JR. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
发明人： James J. Allen, JR. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
IPC分类号： G06F12/02
CPC分类号： G06F12/0862
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to the storage device that can be speculatively issued, and circuitry for intermixing demand accesses and speculative accesses in accordance with the speculative access threshold.
摘要翻译：提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。该设计结构通常包括计算机系统，其包括CPU，存储设备，用于提供与可推测发布的对存储设备的访问总数的所选百分比相对应的推测访问阈值的电路，以及用于混合需求的电路根据投机访问阈值访问和推测访问。

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