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1. 发明授权

US5822334A High speed initialization system for RAM devices using JTAG loop for providing valid parity bits 失效
标题翻译：用于RAM器件的高速初始化系统，使用JTAG环路提供有效的奇偶校验位
公开(公告)号：US5822334A
公开(公告)日：1998-10-13
申请号：US583377
申请日：1996-01-05
申请人： Bruce Ernest Whittaker , James Henry Jeppesen, III
发明人： Bruce Ernest Whittaker , James Henry Jeppesen, III
IPC分类号： G06F11/10 , G11C29/32 , G06F11/00
CPC分类号： G06F11/1064 , G11C29/32
摘要： A computer network having a Control Processing Module (CPM) maintained by an external Maintenance Subsystem where the CPM has JTAG compatible digital units, but where the Cache Module is not JTAG compatible. Specialized transceivers having Boundary Scan Registers are activated to enable loading of address words in a Tag RAM while concomitantly placing correct initial parity data in a Parity RAM without need to continue communication with the external Maintenance Subsystem. The Boundary Scan Registers in said transceivers are set up to perform as up-counters to sequence through all address locations in the Tag RAM while a Control PAL calculates and places the associated parity values in each corresponding address location in the Parity RAM.
摘要翻译：具有由外部维护子系统维护的控制处理模块（CPM）的计算机网络，其中CPM具有JTAG兼容数字单元，但缓存模块不与JTAG兼容。具有边界扫描寄存器的专用收发器被激活，以便能够在标签RAM中加载地址字，同时将正确的初始奇偶校验数据放置在奇偶校验RAM中，而不需要继续与外部维护子系统进行通信。所述收发器中的边界扫描寄存器设置为执行上计数器，以便在标签RAM中的所有地址位置进行序列化，而控制PAL计算并将相关奇偶校验值放置在奇偶校验RAM中的每个对应的地址位置。

2. 发明授权

US5850513A Processor path emulation system providing fast readout and verification of main memory by maintenance controller interface to maintenance subsystem 失效
标题翻译：处理器路径仿真系统通过维护控制器接口向维护子系统提供对主存储器的快速读出和验证
公开(公告)号：US5850513A
公开(公告)日：1998-12-15
申请号：US583326
申请日：1996-01-05
申请人： Bruce Ernest Whittaker , James Henry Jeppesen, III
发明人： Bruce Ernest Whittaker , James Henry Jeppesen, III
IPC分类号： G01R31/3185 , G06F11/267 , G06F11/00 , G06F13/16
CPC分类号： G06F11/2236 , G01R31/318533
摘要： A central processing module (CPM) uses a data path array interface connecting dual system busses to a main memory module and I/O module. A maintenance controller in the CPM manages a programmable array logic unit controller to read out microcode words in the main memory module to verify their accuracy by comparison with an original data base of microcode words in a flash memory which was earlier pre-loaded from a maintenance subsystem. A high speed auxiliary data bus controlled by the programmable array logic controller, provides a high speed transfer channel for moving the main memory words to the maintenance controller which can then institute a verification procedure for each memory word.
摘要翻译：中央处理模块（CPM）使用将双系统总线连接到主存储器模块和I / O模块的数据路径阵列接口。 CPM中的维护控制器管理可编程阵列逻辑单元控制器以读取主存储器模块中的微代码字，以便与先前从维护预加载的闪存中的微代码字的原始数据库进行比较来验证其准确性子系统。由可编程阵列逻辑控制器控制的高速辅助数据总线提供用于将主存储器字移动到维护控制器的高速传输通道，维护控制器然后可以为每个存储器字提供验证程序。

3. 发明授权

US5737567A Fast write initialization system for microcode RAM via data path array using pre-loaded flash memory an programmable control logic array 失效
标题翻译：通过使用预加载闪存的可编程控制逻辑阵列，通过数据路径阵列快速写入初始化系统
公开(公告)号：US5737567A
公开(公告)日：1998-04-07
申请号：US546650
申请日：1995-10-23
申请人： Bruce Ernest Whittaker , James Henry Jeppesen, III
发明人： Bruce Ernest Whittaker , James Henry Jeppesen, III
IPC分类号： G06F9/24 , G06F9/445 , G06F13/00
CPC分类号： G06F9/4403 , G06F9/24
摘要： A network comprising a central processing module and maintenance subsystem which provides a system for rapid loading of instruction words in a microcode RAM whereby microcode instruction words from the maintenance subsystem are preliminarily loaded into a flash memory in the central processing module. A maintenance controller transfers the microcode instruction words from the flash memory over a transfer bus to a data path array which connects to a processor-instruction memory bus for enabling microcode addresses and data words to be rapidly transferred into a microcode RAM instruction memory. A programmable controller activated by the maintenance controller in the central processing module then regulates the transfer of data to the microcode RAM by providing incrementation of the addresses of the instruction words on an automatic basis and thus relieving the processor of this function. Due to the pre-loading of the microcode instruction words into flash memory of the central processing module, there is provided a rapid loading of the microcode RAM during initialization routines without the need to burden the processor or the maintenance subsystem.
摘要翻译：一种包括中央处理模块和维护子系统的网络，其提供用于在微代码RAM中快速加载指令字的系统，由此来自维护子系统的微代码指令字被预先加载到中央处理模块中的闪速存储器中。维护控制器通过传输总线将来自闪速存储器的微代码指令字传送到连接到处理器指令存储器总线的数据路径阵列，以使微代码地址和数据字能够快速传送到微代码RAM指令存储器。由中央处理模块中的维护控制器激活的可编程控制器然后通过自动地提供指令字的地址的增量来调节数据到微代码RAM的传送，从而减轻处理器的这种功能。由于将微代码指令字预加载到中央处理模块的闪存中，提供了在初始化例程期间快速加载微代码RAM，而不需要对处理器或维护子系统负担。

4. 发明授权

US5708773A JTAG interface system for communicating with compliant and non-compliant JTAG devices 失效
标题翻译： JTAG接口系统，用于与兼容和不兼容的JTAG设备进行通信
公开(公告)号：US5708773A
公开(公告)日：1998-01-13
申请号：US504975
申请日：1995-07-20
申请人： James Henry Jeppesen, III , Kelly Sue St. Clair-Hong
发明人： James Henry Jeppesen, III , Kelly Sue St. Clair-Hong
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/318555 , G01R31/318586
摘要： A system and method for using standard JTAG protocol for testing protocol compliant and non-protocol compliant digital devices without altering the JTAG protocol or the non-compliant device. A specialized Test Access Port Controller controls and monitors the states applied to the non-compliant device in order to eliminate the PAUSE state in the non-compliant device and to limit the Run-Test/Idle state to one clock period.
摘要翻译：一种用于使用标准JTAG协议来测试符合协议和非协议的数字设备的系统和方法，而不改变JTAG协议或不兼容设备。专门的测试访问端口控制器控制和监视应用于非兼容设备的状态，以消除非兼容设备中的暂停状态，并将运行测试/空闲状态限制为一个时钟周期。

5. 发明授权

US5706424A System for fast read and verification of microcode RAM 失效
标题翻译：用于快速读取和验证微码RAM的系统
公开(公告)号：US5706424A
公开(公告)日：1998-01-06
申请号：US546651
申请日：1995-10-23
申请人： Bruce Ernest Whittaker , James Henry Jeppesen, III
发明人： Bruce Ernest Whittaker , James Henry Jeppesen, III
IPC分类号： G06F11/16 , G06F11/273 , G11C29/48 , G06F11/34
CPC分类号： G11C29/48 , G06F11/2733 , G06F11/2736
摘要： A system whereby a microcode RAM in a central processing module can have each microcode word rapidly accessed and transferred to a maintenance controller to compare each accessed microcode word with a corresponding microcode word in a set of microcode words which were pre-loaded in a flash memory.
摘要翻译：中央处理模块中的微代码RAM可以使每个微代码字能够快速访问并传送到维护控制器的系统，以将每个访问的微代码字与预先加载到闪速存储器中的一组微代码字中的对应的微代码字进行比较。

6. 发明授权

US5889959A Fast write initialization method and system for loading channel adapter microcode 失效
标题翻译：快速写入初始化方法和系统，用于加载通道适配器的微码
公开(公告)号：US5889959A
公开(公告)日：1999-03-30
申请号：US583376
申请日：1996-01-05
申请人： Bruce Ernest Whittaker , James Henry Jeppesen, III
发明人： Bruce Ernest Whittaker , James Henry Jeppesen, III
IPC分类号： G06F9/24 , G06F9/445 , G06F13/14 , G06F12/02
CPC分类号： G06F9/4403 , G06F9/24
摘要： A computer network serviced by a maintenance subsystem holds a control processing module (CPM) holding a Data Path Array as interface to a main memory module and I/O Module. A maintenance controller in the CPM has a preloaded Flash Memory unit holding all the necessary operating addresses and data which can be rapidly transferred via a special wide parallel high speed data bus to a data path array unit for subsequent conveyance to a channel microcode block in a main memory module. The operating data include channel microcode data necessary for the I/O Module to communicate with different types of peripheral devices.
摘要翻译：由维护子系统维护的计算机网络保持将数据路径阵列作为与主存储器模块和I / O模块的接口的控制处理模块（CPM）。 CPM中的维护控制器具有预加载的闪存单元，其保存所有必要的操作地址和数据，该数据可以通过特殊的宽并行高速数据总线快速传送到数据路径阵列单元，以便随后传送到通道微码块主内存模块操作数据包括I / O模块与不同类型的外围设备通信所需的通道微码数据。

7. 发明授权

US5706297A System for adapting maintenance operations to JTAG and non-JTAG modules 失效
标题翻译：用于将维护操作调整到JTAG和非JTAG模块的系统
公开(公告)号：US5706297A
公开(公告)日：1998-01-06
申请号：US518948
申请日：1995-08-24
申请人： James Henry Jeppesen, III , Bruce Ernest Whittaker
发明人： James Henry Jeppesen, III , Bruce Ernest Whittaker
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318555 , G01R31/318547 , G01R31/318586
摘要： A digital system which normally initializes and tests non-JTAG logic units is adapted to test JTAG protocol compatible logic units. A JTAG translator unit provides an instruction control register and a Data Register. The Control Register has control bits for selecting Test-Mode-Select and Test Clock signals for the JTAG compatible units and Shift/Hold signals for the non-JTAG compatible logic units. The Data Register supplies diagnostic test bits to registers in both the JTAG and non-JTAG logic units. Additionally, the Control Register can initiate automatic incrementation of addresses to a control state RAM for rapid loading of microcode.
摘要翻译：通常初始化和测试非JTAG逻辑单元的数字系统适用于测试JTAG协议兼容的逻辑单元。 JTAG转换器单元提供指令控制寄存器和数据寄存器。控制寄存器具有用于选择JTAG兼容单元的测试模式选择和测试时钟信号以及非JTAG兼容逻辑单元的移位/保持信号的控制位。数据寄存器将诊断测试位提供给JTAG和非JTAG逻辑单元中的寄存器。此外，控制寄存器可以启动自动递增地址到控制状态RAM，以快速加载微码。

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