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1. 发明授权

US07759807B2 Semiconductor package having structure for warpage prevention 有权
标题翻译：具有防翘曲结构的半导体封装
公开(公告)号：US07759807B2
公开(公告)日：2010-07-20
申请号：US11754492
申请日：2007-05-29
申请人： Han Jun Bae , Jae Myun Kim
发明人： Han Jun Bae , Jae Myun Kim
IPC分类号： H01L23/29 , H01L21/50
CPC分类号： H01L23/3114 , H01L23/13 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L2224/32225 , H01L2224/451 , H01L2224/4824 , H01L2224/73215 , H01L2924/00014 , H01L2924/15311 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor package includes a substrate having a plurality of connection pads and a plurality of ball lands; a semiconductor chip attached to one surface of the substrate and having a plurality of bonding pads that are connected to the respective connection pads of the substrate; a first molding structure covering an upper surface of the substrate including a connection region between the bonding pads and the connection pads and the semiconductor chip; a second molding structure formed adjacent to an edge of the lower surface of the substrate; and a plurality of solder balls attached to the respective ball lands of the substrate.
摘要翻译：半导体封装包括具有多个连接焊盘和多个焊盘的衬底; 半导体芯片，其附接到所述基板的一个表面，并且具有连接到所述基板的各个连接焊盘的多个焊盘; 覆盖所述基板的上表面的第一模制结构，包括所述焊盘与所述连接焊盘和所述半导体芯片之间的连接区域; 与所述基板的下表面的边缘相邻形成的第二模制结构; 以及附接到基板的相应球台的多个焊球。

2. 发明申请

US20090001542A1 SEMICONDUCTOR PACKAGE AND MULTI-CHIP SEMICONDUCTOR PACKAGE USING THE SAME 有权
标题翻译：半导体封装和使用相同的多芯片半导体封装
公开(公告)号：US20090001542A1
公开(公告)日：2009-01-01
申请号：US11852425
申请日：2007-09-10
申请人： Jae Myun KIM
发明人： Jae Myun KIM
IPC分类号： H01L23/488
CPC分类号： H01L24/10 , H01L23/3128 , H01L23/49827 , H01L23/49838 , H01L23/525 , H01L24/13 , H01L24/81 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/13 , H01L2224/13099 , H01L2224/16225 , H01L2224/81801 , H01L2225/06517 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2225/06572 , H01L2924/00014 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/15311 , H01L2924/19041 , H01L2924/19043 , H01L2924/00 , H01L2224/05599 , H01L2224/05099
摘要： Disclosed is a semiconductor package and a multi-chip semiconductor package. The semiconductor package includes a semiconductor chip having bonding pads located at a center portion thereof; redistribution patterns extending from the bonding pads toward one edge of the semiconductor chip; and dummy bump pads located adjacent to another edge of the semiconductor chip which is opposite the one edge.
摘要翻译：公开了半导体封装和多芯片半导体封装。半导体封装包括具有位于其中心部分的焊盘的半导体芯片; 从所述接合焊盘向所述半导体芯片的一个边缘延伸的再分布图案; 以及与半导体芯片的与一个边缘相对的另一个边缘相邻的虚设凸块。

3. 发明申请

US20080054434A1 SEMICONDUCTOR STACK PACKAGE FOR OPTIMAL PACKAGING OF COMPONENTS HAVING INTERCONNECTIONS 审中-公开
标题翻译：用于具有互连的组件的最佳包装的半导体堆叠包
公开(公告)号：US20080054434A1
公开(公告)日：2008-03-06
申请号：US11777420
申请日：2007-07-13
申请人： Jae Myun KIM
发明人： Jae Myun KIM
IPC分类号： H01L23/02
CPC分类号： H01L25/105 , H01L23/3128 , H01L2224/06136 , H01L2224/32145 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2225/1023 , H01L2225/1052 , H01L2924/15311 , H01L2924/00
摘要： A stack package comprises a first semiconductor package having a substrate which is formed with a plurality of conductive patterns on a lower surface thereof and with an insulation layer on the lower surface thereof including the conductive patterns, the insulation layer having grooves for exposing the portions of the conductive patterns disposed at least both end portions of the substrate; a second semiconductor package located below the first semiconductor package and having the same structure as the first semiconductor package; conductive adhesives formed on the exposed end portions of the conductive patterns of the first and second semiconductor packages; and a plurality of clip-shaped conductors clipped on both ends of the second semiconductor package and having first ends and second ends which electrically and mechanically connect the conductive patterns of the first semiconductor package and the conductive patterns of the second semiconductor package to each other via the conductive adhesives.
摘要翻译：一种堆叠封装包括：第一半导体封装，其具有在其下表面上形成有多个导电图案的基板，并且在其下表面上具有包括导电图案的绝缘层，所述绝缘层具有用于暴露部分的凹槽所述导电图案至少设置在所述基板的两个端部; 位于所述第一半导体封装之下并具有与所述第一半导体封装相同结构的第二半导体封装; 形成在第一和第二半导体封装的导电图案的暴露端部上的导电粘合剂; 以及夹在所述第二半导体封装的两端上的多个夹形导体，并且具有将所述第一半导体封装的所述导电图案与所述第二半导体封装的所述导电图案电连接和机械连接的第一端和第二端，所述第二端和所述第二端经由导电胶。

4. 发明授权

US6121682A Multi-chip package 有权
标题翻译：多芯片封装
公开(公告)号：US6121682A
公开(公告)日：2000-09-19
申请号：US469131
申请日：1999-12-21
申请人： Jae Myun Kim
发明人： Jae Myun Kim
IPC分类号： H01L23/28 , H01L21/98 , H01L25/065 , H01L23/48
CPC分类号： H01L25/50 , H01L25/0657 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/1403 , H01L2224/16145 , H01L2224/48091 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/30107
摘要： Disclosed is a multi-chip package. According to the present invention, a first semiconductor chip includes a first face in which a bonding pad disposed, and a second face opposite to the first face. A first insulating layer is coated over the first face of the first semiconductor chip so as to expose the bonding pad. A metal pattern is deposited on the first insulating layer and one end of the metal pattern is connected to the exposed bonding pad. A second insulating layer having a via hole exposing the metal pattern and a ball land, is coated over the first face of the first semiconductor chip. A second semiconductor chip includes a first face in which a bonding pad is disposed and opposite to the first face of the first semiconductor chip, and a second face opposite to the first face of the second semiconductor chip. The second semiconductor chip is opposed from the first face of the first semiconductor chip by a selected distance. A third insulating layer is coated on the first face of the second semiconduuctor chip so as to expose the bonding pad of the second semiconductor chip. A conductive bump is formed at the bonding pad of the second semiconductor chip. The conductive bump is inserted into the via hole, thereby electrically connecting the first and the second semiconductor chips with a medium of the metal pattern. A solder ball is mounted in the ball land, and the solder ball is formed with a size that is large enough to be protruded from the second face of the second semiconductor layer.
摘要翻译：公开了一种多芯片封装。根据本发明，第一半导体芯片包括其中布置有焊盘的第一面和与第一面相对的第二面。第一绝缘层涂覆在第一半导体芯片的第一面上，以露出接合焊盘。金属图案沉积在第一绝缘层上，并且金属图案的一端连接到暴露的焊盘。具有暴露金属图案和球面的通孔的第二绝缘层涂覆在第一半导体芯片的第一面上。第二半导体芯片包括第一面，其中焊盘设置并与第一半导体芯片的第一面相对，第二面与第二半导体芯片的第一面相对。第二半导体芯片与第一半导体芯片的第一面相隔一定距离。第三绝缘层涂覆在第二半导体芯片的第一面上，以露出第二半导体芯片的焊盘。在第二半导体芯片的接合焊盘处形成导电凸块。将导电凸块插入到通孔中，从而将第一和第二半导体芯片与金属图案的介质电连接。焊球安装在球场中，焊球形成的尺寸足够大以从第二半导体层的第二面突出。

5. 发明授权

US08242582B2 Semiconductor package and stacked semiconductor package having the same 有权
标题翻译：具有相同的半导体封装和堆叠半导体封装
公开(公告)号：US08242582B2
公开(公告)日：2012-08-14
申请号：US12647657
申请日：2009-12-28
申请人： Bok Gyu Min , Jae Myun Kim , Da Un Nah
发明人： Bok Gyu Min , Jae Myun Kim , Da Un Nah
IPC分类号： H01L23/00
CPC分类号： H01L23/3128 , H01L24/48 , H01L25/0657 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a semiconductor chip possessing a shape with corners and has a circuit section. The semiconductor chip has one or more chamfered portions which are formed in a first corner group that includes one or more of the corners. Data bonding pads are disposed on the semiconductor chip and are electrically connected to the circuit section. A chip selection pad is disposed adjacent to a second corner group that includes at least one of the corners which is not formed with a chamfered portion. The chip selection pad is electrically connected to the circuit section. A plurality of the semiconductor packages may be stacked so that the chip selection pad of one of the semiconductor packages is left exposed when another semiconductor package is stacked thereover due to the chamfered portion of the other semiconductor package.
摘要翻译：半导体封装包括具有拐角形状并具有电路部分的半导体芯片。半导体芯片具有形成在包括一个或多个拐角的第一角组中的一个或多个倒角部分。数据接合焊盘设置在半导体芯片上并与电路部分电连接。芯片选择焊盘被布置成与包括未形成有倒角部分的角部中的至少一个的第二角部组相邻。芯片选择板电连接到电路部分。可以堆叠多个半导体封装，使得当另一个半导体封装由于另一个半导体封装的倒角部分堆叠而使半导体封装中的一个的芯片选择焊盘露出。

6. 发明授权

US07825504B2 Semiconductor package and multi-chip semiconductor package using the same 有权
标题翻译：半导体封装和多芯片半导体封装采用相同
公开(公告)号：US07825504B2
公开(公告)日：2010-11-02
申请号：US11852425
申请日：2007-09-10
申请人： Jae Myun Kim
发明人： Jae Myun Kim
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L24/10 , H01L23/3128 , H01L23/49827 , H01L23/49838 , H01L23/525 , H01L24/13 , H01L24/81 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/13 , H01L2224/13099 , H01L2224/16225 , H01L2224/81801 , H01L2225/06517 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2225/06572 , H01L2924/00014 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/15311 , H01L2924/19041 , H01L2924/19043 , H01L2924/00 , H01L2224/05599 , H01L2224/05099
摘要： Disclosed is a semiconductor package and a multi-chip semiconductor package. The semiconductor package includes a semiconductor chip having bonding pads located at a center portion thereof; redistribution patterns extending from the bonding pads toward one edge of the semiconductor chip; and dummy bump pads located adjacent to another edge of the semiconductor chip which is opposite the one edge.
摘要翻译：公开了半导体封装和多芯片半导体封装。半导体封装包括具有位于其中心部分的焊盘的半导体芯片; 从所述接合焊盘向所述半导体芯片的一个边缘延伸的再分布图案; 以及与半导体芯片的与一个边缘相对的另一个边缘相邻的虚设凸块。

7. 发明申请

US20090065924A1 SEMICONDUCTOR PACKAGE WITH REDUCED VOLUME AND SIGNAL TRANSFER PATH 审中-公开
标题翻译：具有减少体积和信号传输路径的半导体封装
公开(公告)号：US20090065924A1
公开(公告)日：2009-03-12
申请号：US12058955
申请日：2008-03-31
申请人： Jae Myun KIM , Byeong Yong LIM
发明人： Jae Myun KIM , Byeong Yong LIM
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/05599 , H01L2224/06133 , H01L2224/06135 , H01L2224/16 , H01L2225/06517 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01014 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/014 , H01L2924/15311
摘要： A semiconductor package includes a first semiconductor chip having a first semiconductor chip body including a first circuit region and peripheral regions arranged around the first circuit region. A first bonding pad group is arranged within the first circuit region and includes a plurality of bonding pads. A first redistribution group including a plurality of redistributions is electrically connected to the respective bonding pads and extends towards the peripheral regions. The package further includes a second semiconductor chip having a second semiconductor chip body including a second circuit region opposing the first circuit region. A second bonding pad group is arranged within the second circuit region and corresponds to the first bonding pad group. A second redistribution group is electrically connected to the respective bonding pads of the second bonding pad group. Redistribution connection members are used to electrically connect the first redistribution group to the second redistribution group.
摘要翻译：半导体封装包括具有第一半导体芯片本体的第一半导体芯片，第一半导体芯片主体包括第一电路区域和围绕第一电路区域布置的外围区第一焊盘组布置在第一电路区域内并且包括多个焊盘。包括多个再分布的第一再分布组电连接到相应的接合焊盘并朝着周边区域延伸。该封装还包括具有第二半导体芯片本体的第二半导体芯片，该第二半导体芯片主体包括与第一电路区域相对的第二电路区域。第二接合焊盘组布置在第二电路区域内，并对应于第一接合焊盘组。第二再分布组电连接到第二接合焊盘组的各个接合焊盘。再分配连接构件用于将第一再分配组电连接到第二再分配组。

8. 发明授权

US06380629B1 Wafer level stack package and method of fabricating the same 有权
标题翻译：晶圆级堆叠封装及其制造方法
公开(公告)号：US06380629B1
公开(公告)日：2002-04-30
申请号：US09595113
申请日：2000-06-16
申请人： Jae Myun Kim
发明人： Jae Myun Kim
IPC分类号： H01L2348
CPC分类号： H01L25/50 , H01L25/0657 , H01L2224/48091 , H01L2224/48247 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06586 , H01L2924/01079 , H01L2924/00014
摘要： A wafer level stack package according to the present invention has upper and lower semiconductor chips stacked together in a wafer level. Each chip has a first face where bond pads are formed and an opposite second face. The first faces confront each other in a stack. In each chip, metal patterns are connected to the bond pads and intervene between insulating layers. Through holes are formed at both sides of the upper chip, and a pattern film is adhered to the second face of the upper chip. The metal patterns are exposed in the through holes and electrically connected to solder balls on the pattern film. A related method is also provided.
摘要翻译：根据本发明的晶片级堆叠封装具有在晶片级堆叠在一起的上半导体芯片和下半导体芯片。每个芯片具有形成接合焊盘的第一面和相对的第二面。第一个面对面互相堆叠。在每个芯片中，金属图案连接到接合焊盘并且介于绝缘层之间。在上部芯片的两侧形成通孔，并且图案膜粘附到上部芯片的第二面。金属图案暴露在通孔中并电连接到图案膜上的焊球。还提供了相关的方法。

9. 发明授权

US09064862B2 Semiconductor chips having a dual-layered structure, packages having the same, and methods of fabricating the semiconductor chips and the packages 有权
标题翻译：具有双层结构的半导体芯片，具有相同的封装，以及制造半导体芯片和封装的方法
公开(公告)号：US09064862B2
公开(公告)日：2015-06-23
申请号：US13564431
申请日：2012-08-01
申请人： In Chul Hwang , Jae Myun Kim , Seung Jee Kim , Jin Su Lee
发明人： In Chul Hwang , Jae Myun Kim , Seung Jee Kim , Jin Su Lee
IPC分类号： H01L21/50 , H01L25/00 , H01L21/768 , H01L25/065 , H01L23/00
CPC分类号： H01L25/50 , H01L21/76898 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L2224/0401 , H01L2224/08145 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/48227 , H01L2224/80006 , H01L2224/80896 , H01L2224/81191 , H01L2224/9202 , H01L2224/9222 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2924/10253 , H01L2924/12041 , H01L2924/00 , H01L2224/80 , H01L2224/11 , H01L2224/81
摘要： Dual-layered structural semiconductor chips are provided. The semiconductor chip includes a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. The first semiconductor chip includes a first substrate having a first bottom surface. The second semiconductor chip includes a second substrate having a second bottom surface. The first bottom surface directly contacts the second bottom surface. The related packages and the related methods are also provided.
摘要翻译：提供双层结构半导体芯片。半导体芯片包括接合到第一半导体芯片的第一半导体芯片和第二半导体芯片。第一半导体芯片包括具有第一底表面的第一基板。第二半导体芯片包括具有第二底面的第二基板。第一底面直接接触第二底面。还提供了相关包和相关方法。

10. 发明申请

US20130037942A1 SEMICONDUCTOR CHIPS HAVING A DUAL-LAYERED STRUCTURE, PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR CHIPS AND THE PACKAGES 有权
公开(公告)号：US20130037942A1
公开(公告)日：2013-02-14
申请号：US13564431
申请日：2012-08-01
申请人： In Chul HWANG , Jae Myun KIM , Seung Jee KIM , Jin Su LEE
发明人： In Chul HWANG , Jae Myun KIM , Seung Jee KIM , Jin Su LEE
IPC分类号： H01L23/498 , H01L23/48 , H01L21/50
CPC分类号： H01L25/50 , H01L21/76898 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L2224/0401 , H01L2224/08145 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/48227 , H01L2224/80006 , H01L2224/80896 , H01L2224/81191 , H01L2224/9202 , H01L2224/9222 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2924/10253 , H01L2924/12041 , H01L2924/00 , H01L2224/80 , H01L2224/11 , H01L2224/81
摘要： Dual-layered structural semiconductor chips are provided. The semiconductor chip includes a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. The first semiconductor chip includes a first substrate having a first bottom surface. The second semiconductor chip includes a second substrate having a second bottom surface. The first bottom surface directly contacts the second bottom surface. The related packages and the related methods are also provided.

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