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1. 发明授权

US06735588B2 Information search method and apparatus using Inverse Hidden Markov Model 有权
标题翻译：使用反隐马尔可夫模型的信息搜索方法和装置
公开(公告)号：US06735588B2
公开(公告)日：2004-05-11
申请号：US09853649
申请日：2001-05-14
申请人： Bo-Sung Kim , Jun-dong Cho , Young-hoon Chang , Sun-hee Park
发明人： Bo-Sung Kim , Jun-dong Cho , Young-hoon Chang , Sun-hee Park
IPC分类号： G06F1730
CPC分类号： G06K9/6297 , G10L15/142 , G10L15/144 , Y10S707/99935
摘要： An information search method and apparatus employ an Inverse Hidden Markov Model (IHMM) for stochastically searching for a reference information model among a plurality of predetermined reference information models obtained by training that best matches unknown information which is expressed by a Hidden Markov Model (HMM) chain. The method and apparatus find an optimal path in a HMM state lattice using a minimum unlikelihood score, rather than a maximum likelihood score, and using a Viterbi algorithm, to recognize unknown information, so that unnecessary computations are avoided. The method and apparatus can be used for finding the most likely path through a vocabulary network for a given utterance.
摘要翻译：信息搜索方法和装置采用逆隐马尔可夫模型（IHMM）来随机搜索通过训练获得的多个预定参考信息模型中的参考信息模型，所述参考信息模型与由隐马尔可夫模型（HMM）表示的未知信息最佳匹配，链。该方法和装置使用最小不可能得分而不是最大似然分数在HMM状态网格中找到最佳路径，并使用维特比算法来识别未知信息，从而避免不必要的计算。该方法和装置可以用于通过用于给定话语的词汇网络找到最可能的路径。

2. 发明申请

US20090144480A1 MULTI-PROCESSOR SYSTEM ON CHIP PLATFORM AND DVB-T BASEBAND RECEIVER USING THE SAME 审中-公开
标题翻译：使用芯片平台的多处理器系统和使用其的DVB-T基带接收器
公开(公告)号：US20090144480A1
公开(公告)日：2009-06-04
申请号：US11949716
申请日：2007-12-03
申请人： JUN-DONG CHO , Koon Shik , Seung Hoon Lee , Jong Chul Kim , Byung Joo Hong , Suk Yun Lee
发明人： JUN-DONG CHO , Koon Shik , Seung Hoon Lee , Jong Chul Kim , Byung Joo Hong , Suk Yun Lee
IPC分类号： G06F13/00
CPC分类号： G06F15/7842 , G06F15/17375
摘要： A multi-processor system on chip (SoC) platform and a DVB-T baseband receiver using the same are disclosed. The multi-processor SoC platform includes a first processor, at least one second processor, at least one slave device communicating with the first processor and the second processor and a communication interface (CI) unit connecting the slave device to the first processor and the second processor according to a cross-bar switching method to allow the slave device to be communicated with the first processor and the second processor. Therefore, the multi-processor SoC platform having flexibility with being adapted for high speed calculation by using a cross-bar switch is provided.
摘要翻译：公开了一种多处理器片上系统（SoC）平台和使用其的DVB-T基带接收机。所述多处理器SoC平台包括第一处理器，至少一个第二处理器，与所述第一处理器和所述第二处理器通信的至少一个从设备以及将所述从设备连接到所述第一处理器和所述第二处理器的通信接口（CI）单元处理器，以便允许从设备与第一处理器和第二处理器通信。因此，提供了具有灵活性的多处理器SoC平台，其适用于通过使用横杆开关进行高速计算。

3. 发明授权

US06480991B1 Timing-driven global placement based on geometry-aware timing budgets 有权
标题翻译：基于几何感知时序预算的定时驱动的全局放置
公开(公告)号：US06480991B1
公开(公告)日：2002-11-12
申请号：US09832623
申请日：2001-04-11
申请人： Jun-Dong Cho , David S. Kung
发明人： Jun-Dong Cho , David S. Kung
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A system and method for timing-closed placement which also takes wirelength and congestion into consideration. In one aspect, the system and method of timing driven placement according to the present invention incorporates a timing budget management technique which satisfies triangle parity and inequality, a timing-driven quadrisection placement strategy based on flexible timing window configurations to minimize the wirelength and congestion during each mincut quad-partition of top-down hierarchy, and a linear programming formulation incorporating bin capacity, channel capacity and congestion criticality.
摘要翻译：定时关闭放置的系统和方法，也考虑了线长和拥塞。在一个方面，根据本发明的定时驱动放置的系统和方法包括满足三角奇偶校验和不等式的定时预算管理技术，基于灵活的定时窗口配置的时序驱动四分位放置策略，以最小化线长度和拥塞每个最小分割自上而下的四分区，以及包含容量，信道容量和拥塞关键性的线性规划公式。

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