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1. 发明授权

US09798541B2 Apparatus and method for propagating conditionally evaluated values in SIMD/vector execution using an input mask register 有权
公开(公告)号：US09798541B2
公开(公告)日：2017-10-24
申请号：US13997183
申请日：2011-12-23
申请人： Jayashankar Bharadwaj , Nalini Vasudevan , Victor W. Lee , Daehyun Kim , Albert Hartono , Sara S. Baghsorkhi
发明人： Jayashankar Bharadwaj , Nalini Vasudevan , Victor W. Lee , Daehyun Kim , Albert Hartono , Sara S. Baghsorkhi
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30098 , G06F9/30192 , G06F9/3877
摘要： An apparatus and method for propagating conditionally evaluated values are disclosed. For example, a method according to one embodiment comprises: reading each value contained in an input mask register, each value being a true value or a false value and having a bit position associated therewith; for each true value read from the input mask register, generating a first result containing the bit position of the true value; for each false value read from the input mask register following the first true value, adding the vector length of the input mask register to a bit position of the last true value read from the input mask register to generate a second result; and storing each of the first results and second results in bit positions of an output register corresponding to the bit positions read from the input mask register.

2. 发明申请

US20140223139A1 SYSTEMS, APPARATUSES, AND METHODS FOR SETTING AN OUTPUT MASK IN A DESTINATION WRITEMASK REGISTER FROM A SOURCE WRITE MASK REGISTER USING AN INPUT WRITEMASK AND IMMEDIATE 有权
标题翻译：用于使用输入写入和立即从源写入掩码寄存器设置目的地写入寄存器中的输出掩码的系统，设备和方法
公开(公告)号：US20140223139A1
公开(公告)日：2014-08-07
申请号：US13991877
申请日：2011-12-23
申请人： Victor W. Lee , Daehyun Kim , Tin-Fook Ngai , Jayashankar Bharadwaj , Albert Hartono , Sara Baghsorkhi , Nalini Vasudevan
发明人： Victor W. Lee , Daehyun Kim , Tin-Fook Ngai , Jayashankar Bharadwaj , Albert Hartono , Sara Baghsorkhi , Nalini Vasudevan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30025 , G06F9/30072 , G06F15/8007 , G06F15/8053 , G06F15/8084 , G06F15/8092
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.
摘要翻译：描述了用于在计算机处理器中执行基于向量比较响应于单个指令生成谓词掩码的系统，装置和方法的实施例。

3. 发明申请

US20130275724A1 SYSTEMS, APPARATUSES, AND METHODS FOR GENERATING A DEPENDENCY VECTOR BASED ON TWO SOURCE WRITEMASK REGISTERS 有权
标题翻译：基于两个源代码写入寄存器生成依赖矢量的系统，设备和方法
公开(公告)号：US20130275724A1
公开(公告)日：2013-10-17
申请号：US13992707
申请日：2011-12-27
申请人： Jayashankar Bharadwaj
发明人： Jayashankar Bharadwaj
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30018 , G06F9/30036 , G06F9/30065 , G06F9/30098 , G06F9/30145
摘要： Embodiments of systems, apparatuses, and methods of performing in a computer processor dependency index vector calculation in response to an instruction that includes a first and second source writemask register operands, a destination vector register operand, and an opcode are described.
摘要翻译：描述了响应于包括第一和第二源写入寄存器操作数，目的地向量寄存器操作数和操作码的指令在计算机处理器依赖性索引向量计算中执行的系统，装置和方法的实施例。

4. 发明申请

US20140189323A1 APPARATUS AND METHOD FOR PROPAGATING CONDITIONALLY EVALUATED VALUES IN SIMD/VECTOR EXECUTION 有权
标题翻译：在SIMD / VECTOR执行中传播有条件评估值的装置和方法
公开(公告)号：US20140189323A1
公开(公告)日：2014-07-03
申请号：US13997183
申请日：2011-12-23
申请人： Jayashankar Bharadwaj , Nalini Vasudevan , Victor W. Lee , Daehyun Kim , Albert Hartono , Sara S. Baghsorkhi
发明人： Jayashankar Bharadwaj , Nalini Vasudevan , Victor W. Lee , Daehyun Kim , Albert Hartono , Sara S. Baghsorkhi
IPC分类号： G06F9/30
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30098 , G06F9/30192 , G06F9/3877
摘要： An apparatus and method for propagating conditionally evaluated values. For example, a method according to one embodiment comprises: reading each value contained in an input mask register, each value being a true value or a false value and having a bit position associated therewith; for each true value read from the input mask register, generating a first result containing the bit position of the true value; for each false value read from the input mask register following the first true value, adding the vector length of the input mask register to a bit position of the last true value read from the input mask register to generate a second result; and storing each of the first results and second results in bit positions of an output register corresponding to the bit positions read from the input mask register.
摘要翻译：用于传播有条件评估值的装置和方法。例如，根据一个实施例的方法包括：读取输入屏蔽寄存器中包含的每个值，每个值是真值或假值，并具有与其相关联的位位置; 对于从输入掩码寄存器读取的每个真值，生成包含真值的位位置的第一结果; 对于从输入屏蔽寄存器读取的每个错误值跟随第一个真实值，将输入屏蔽寄存器的向量长度加到从输入屏蔽寄存器读取的最后一个真值的位位置，以产生第二个结果; 并将每个第一结果和第二结果存储在与从输入屏蔽寄存器读取的位位置对应的输出寄存器的位位置中。

5. 发明申请

US20140096119A1 LOOP VECTORIZATION METHODS AND APPARATUS 有权
标题翻译： LOOP VECTORIZATION方法和装置
公开(公告)号：US20140096119A1
公开(公告)日：2014-04-03
申请号：US13630147
申请日：2012-09-28
申请人： NALINI VASUDEVAN , JAYASHANKAR BHARADWAJ , CHRISTOPHER J. HUGHES , MILIND B. GIRKAR , MARK J. CHARNEY , ROBERT VALENTINE , VICTOR W. LEE , DAEHYUN KIM , ALBERT HARTONO , SARA S. BAGHSORKHI
发明人： NALINI VASUDEVAN , JAYASHANKAR BHARADWAJ , CHRISTOPHER J. HUGHES , MILIND B. GIRKAR , MARK J. CHARNEY , ROBERT VALENTINE , VICTOR W. LEE , DAEHYUN KIM , ALBERT HARTONO , SARA S. BAGHSORKHI
IPC分类号： G06F9/44
CPC分类号： G06F8/443 , G06F8/433 , G06F8/452 , G06F8/70 , G06F9/30036 , G06F9/38 , G06F9/3836
摘要： Loop vectorization methods and apparatus are disclosed. An example method includes setting a dynamic adjustment value of a vectorization loop; executing the vectorization loop to vectorize a loop by grouping iterations of the loop into one or more vectors; identifying a dependency between iterations of the loop as; and setting the dynamic adjustment value based on the identified dependency.
摘要翻译：公开了环向量化方法和装置。示例性方法包括设置矢量化循环的动态调整值; 执行向量化循环以通过将循环的迭代分组为一个或多个向量来矢量化循环; 识别循环迭代之间的依赖关系; 并且基于所识别的依赖关系来设置动态调整值。

6. 发明授权

US07240342B1 User transparent continuous compilation 有权
标题翻译：用户透明连续编译
公开(公告)号：US07240342B1
公开(公告)日：2007-07-03
申请号：US09608616
申请日：2000-06-30
申请人： Jayashankar Bharadwaj , Ravi Narayanaswamy
发明人： Jayashankar Bharadwaj , Ravi Narayanaswamy
IPC分类号： G06F9/44
CPC分类号： G06F8/41 , G06F9/45525
摘要： According to one embodiment, systems, apparatus and methods are disclosed for installing a program onto a target machine, executing the program, and responsive to a change in profile data collected while the program executes which exceeds a predetermined threshold, recompiling the program while the target machine is idle.
摘要翻译：根据一个实施例，公开了系统，装置和方法，用于将程序安装到目标机器上，执行程序，并且响应于程序执行时收集的简档数据的变化超过预定阈值，重新编译程序，而目标机器空闲

7. 发明授权

US06446258B1 Interactive instruction scheduling and block ordering 失效
标题翻译：交互式指令调度和块排序
公开(公告)号：US06446258B1
公开(公告)日：2002-09-03
申请号：US09185422
申请日：1998-11-03
申请人： Christopher M. McKinsey , Jayashankar Bharadwaj
发明人： Christopher M. McKinsey , Jayashankar Bharadwaj
IPC分类号： G06F945
CPC分类号： G06F8/445
摘要： In some embodiments, the invention includes a method of compiling instructions of a program. The method includes receiving instructions for code motion and controlling the code motion while interacting with block ordering. The code motion may be done as part of various activities including instruction scheduling, partial redundancy elimination, and loop invariant removal. The scheduling may involve making an assessment of the cost of scheduling an instruction that takes into account generation and/or elimination of branches due to resulting block order update and determining whether to make the code motion based on the cost. Instruction scheduling may involve regeneration of predicate expressions to invert conditional branches.
摘要翻译：在一些实施例中，本发明包括编译程序指令的方法。该方法包括在与块排序交互的同时接收代码运动指令和控制代码运动。代码运动可以作为各种活动的一部分，包括指令调度，部分冗余消除和循环不变量去除。调度可以包括对由于所得到的块顺序更新引起的考虑分支生成和/或消除的指令的调度成本进行评估，并且基于成本确定是否进行代码运动。指令调度可能涉及再生谓词表达式以反转条件分支。

8. 发明授权

US09268626B2 Apparatus and method for vectorization with speculation support 有权
标题翻译：用于推测支持的矢量化装置和方法
公开(公告)号：US09268626B2
公开(公告)日：2016-02-23
申请号：US13997664
申请日：2011-12-23
申请人： Jayashankar Bharadwaj , Victor W. Lee , Kim Daehyun , Nalini Vasudevan , Tin-Fook Ngai , Albert Hartono , Sara S. Baghsorkhi
发明人： Jayashankar Bharadwaj , Victor W. Lee , Kim Daehyun , Nalini Vasudevan , Tin-Fook Ngai , Albert Hartono , Sara S. Baghsorkhi
IPC分类号： G06F11/00 , G06F11/07 , G06F9/30
CPC分类号： G06F11/0751 , G06F9/30018 , G06F9/30036 , G06F9/30043
摘要： An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.
摘要翻译：描述了用于检测和响应处理器中的故障状况的装置和方法。例如，一种方法的一个实施例包括：从第一向量寄存器连续读取每个有源元件，每个有源元件指定用于集合或加载操作的地址; 检测与一个或多个所述有源元件相关联的一个或多个故障状况; 对于在除了所述第一有源元件之外的元件的检测到的故障状况之前连续读取的每个有源元件，将从与所述有源元件相关联的地址加载的数据存储在第一输出向量寄存器中; 并且对于与检测到的故障状况相关联的每个有源元件并且跟随检测到的故障状况，设置输出屏蔽寄存器中的位以指示检测到的故障状况。

9. 发明申请

US20140189288A1 INSTRUCTION TO REDUCE ELEMENTS IN A VECTOR REGISTER WITH STRIDED ACCESS PATTERN 有权
标题翻译：指示减少具有强力访问模式的矢量寄存器中的元件
公开(公告)号：US20140189288A1
公开(公告)日：2014-07-03
申请号：US13993653
申请日：2012-12-28
申请人： Albert Hartono , Jayashankar Bharadwaj , Nalini Vasudevan , Sara S. Baghsorkhi , Victor W. Lee , Daehyun Kim
发明人： Albert Hartono , Jayashankar Bharadwaj , Nalini Vasudevan , Sara S. Baghsorkhi , Victor W. Lee , Daehyun Kim
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30018 , G06F9/30065 , G06F9/3455
摘要： A vector reduction instruction with non-unit strided access pattern is received and executed by the execution circuitry of a processor. In response to the instruction, the execution circuitry performs an associative reduction operation on data elements of a first vector register. Based on values of the mask register and a current element position being processed, the execution circuitry sequentially set one or more data elements of the first vector register to a result, which is generated by the associative reduction operation applied to both a previous data element of the first vector register and a data clement of a third vector register. The previous data element is located more than one element position away from the current element position.
摘要翻译：由处理器的执行电路接收并执行具有非单位步进访问模式的向量减少指令。响应于该指令，执行电路对第一向量寄存器的数据元素执行关联缩减操作。基于屏蔽寄存器的值和正在处理的当前元件位置，执行电路顺序地将第一向量寄存器的一个或多个数据元素设置为结果，该结果是通过应用于先前的数据元素第一向量寄存器和第三向量寄存器的数据元素。先前的数据元素位于远离当前元素位置的多个元素位置。

10. 发明申请

US20130311530A1 APPARATUS AND METHOD FOR SELECTING ELEMENTS OF A VECTOR COMPUTATION 审中-公开
标题翻译：选择矢量计算要素的装置和方法
公开(公告)号：US20130311530A1
公开(公告)日：2013-11-21
申请号：US13992530
申请日：2012-03-30
申请人： Victor W. Lee , Jayashankar Bharadwaj , Daehyun Kim , Nalini Vasudevan , Tin-Fook Ngai , Albert Hartono , Sara Baghsorkhi
发明人： Victor W. Lee , Jayashankar Bharadwaj , Daehyun Kim , Nalini Vasudevan , Tin-Fook Ngai , Albert Hartono , Sara Baghsorkhi
IPC分类号： G06F7/548
CPC分类号： G06F7/548 , G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3877 , G06F9/3895
摘要： An apparatus and method are described for performing a vector reduction. For example, an apparatus according to one embodiment comprises: a reduction logic tree comprised of a set of N-1 reduction logic blocks used to perform reduction in a single operation cycle for N vector elements; a first input vector register storing a first input vector communicatively coupled to the set of reduction logic blocks; a second input vector register storing a second input vector communicatively coupled to the set of reduction logic blocks; a mask register storing a mask value controlling a set of one or more multiplexers, each of the set of multiplexers selecting a value directly from the first input vector register or an output containing a processed value from one of the reduction logic blocks; and an output vector register coupled to outputs of the one or more multiplexers to receive values output passed through by each of the multiplexers responsive to the control signals.
摘要翻译：描述了用于执行向量减少的装置和方法。例如，根据一个实施例的装置包括：还原逻辑树，包括用于对N个向量元素执行单个操作周期的减少的一组N-1减少逻辑块; 存储通信地耦合到所述一组还原逻辑块的第一输入向量的第一输入向量寄存器; 存储通信地耦合到所述一组减少逻辑块的第二输入向量的第二输入向量寄存器; 屏蔽寄存器，其存储控制一个或多个多路复用器的集合的掩码值，所述多路复用器集合中的每一个直接从所述第一输入向量寄存器选择值，或者包含来自所述还原逻辑块之一的处理值的输出; 以及耦合到所述一个或多个多路复用器的输出的输出矢量寄存器，以响应于所述控制信号接收由所述多路复用器中的每一个通过的值。

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