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1. 发明申请

US20090283876A1 ELECTROMAGNETIC INTERFERENCE SHIELD FOR SEMICONDUCTORS USING A CONTINUOUS OR NEAR-CONTINUOUS PERIPHERAL CONDUCTING SEAL AND A CONDUCTING LID 失效
标题翻译：使用连续或近乎连续的外围导电密封和导电引线的半导体的电磁干扰屏蔽
公开(公告)号：US20090283876A1
公开(公告)日：2009-11-19
申请号：US12119654
申请日：2008-05-13
申请人： J. Richard Behun , Erwin B. Cohen
发明人： J. Richard Behun , Erwin B. Cohen
IPC分类号： H01L23/552 , H01L21/58
CPC分类号： H01L23/552 , H01L23/04 , H01L23/10 , H01L24/16 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/16315 , H01L2924/166 , H01L2924/3025
摘要： A semiconductor package structure including a conductive adhesive material which is used to form an electromagnetic interference shield-forming Faraday cage. The Faraday cage incorporates a module lid as the top surface thereof, the conductive material as the sides and a laminate ground plane(s) or substrate as its bottom. Also disclosed is a method for fabricating the foregoing semiconductor package structure.
摘要翻译：一种半导体封装结构，包括用于形成电磁干扰屏蔽成形法拉第笼的导电粘合剂材料。法拉第笼包含模块盖作为其顶表面，导电材料作为侧面，并且层压接地平面或基底作为其底部。还公开了制造上述半导体封装结构的方法。

2. 发明授权

US08044512B2 Electrical property altering, planar member with solder element in IC chip package 有权
标题翻译：电性能改变，平板元件与焊锡元件集成在IC芯片封装中
公开(公告)号：US08044512B2
公开(公告)日：2011-10-25
申请号：US12491438
申请日：2009-06-25
申请人： J. Richard Behun , David B. Stone
发明人： J. Richard Behun , David B. Stone
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/50 , H01L23/49811 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/16 , H01L2224/0401 , H01L2224/05599 , H01L2224/131 , H01L2224/16225 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/19015 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00
摘要： A structure includes a solder element for electrically coupling a substrate of an integrated circuit (IC) chip package and a printed circuit board (PCB); and a first electrical property altering, substantially planar member positioned between the solder element and at least one of a landing pad of the substrate and a landing pad of the PCB. In another embodiment, the electrical property altering, planar member can be applied to the solder element(s) between the IC chip and the package substrate.
摘要翻译：一种结构包括用于电耦合集成电路（IC）芯片封装的衬底和印刷电路板（PCB）的焊料元件; 以及位于所述焊料元件与所述基板的着陆焊盘和所述PCB的着陆焊盘中的至少一个之间的第一电性质改变的基本平坦的构件。在另一个实施例中，电性能改变的平面构件可以被施加到IC芯片和封装衬底之间的焊料元件。

3. 发明授权

US06654488B1 Fill pattern inspection 失效
标题翻译：填充图案检查
公开(公告)号：US06654488B1
公开(公告)日：2003-11-25
申请号：US09346468
申请日：1999-07-01
申请人： J. Richard Behun , Jacek G. Smolinski
发明人： J. Richard Behun , Jacek G. Smolinski
IPC分类号： G06K900
CPC分类号： G03F1/84 , G03F7/70616 , G06T7/0004 , G06T2207/10056 , G06T2207/30148
摘要： Fill pattern inspection system and method where the fill patterns are inspected to a different criteria than the primary pattern or not inspected at all. The fill pattern images are marked such that they may be identified by easily recognizable shapes or designations to avoid unnecessary inspections and repairs in the fill areas. Alternatively, subresolution markers are placed in an image data for locating fill pattern areas. A software tool is also programmed to automatically detect the subresolution markers during inspection and to inspect the regions on a plate which correspond to the subresolution markers in the image data at a different level of criteria than one which is employed for primary pattern inspection.
摘要翻译：填充图案检查系统和方法，其中填充图案被检查到与主要图案不同的标准或根本不被检查。填充图案图像被标记为使得它们可以通过容易识别的形状或指定来识别，以避免在填充区域中进行不必要的检查和修理。或者，将分辨率标记放置在用于定位填充图案区域的图像数据中。软件工具也被编程为在检查过程中自动检测分辨率标记，并以与用于初级图形检查的标准不同的标准水平来检查与图像数据中的分辨率标记对应的板上的区域。

4. 发明申请

US20100327405A1 ELECTRICAL PROPERTY ALTERING, PLANAR MEMBER WITH SOLDER ELEMENT IN IC CHIP PACKAGE 有权
标题翻译：电气设备改造，带有芯片包装中的焊接元件的平面构件
公开(公告)号：US20100327405A1
公开(公告)日：2010-12-30
申请号：US12491438
申请日：2009-06-25
申请人： J. Richard Behun , David B. Stone
发明人： J. Richard Behun , David B. Stone
IPC分类号： H01L27/10 , H01L21/50
CPC分类号： H01L23/50 , H01L23/49811 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/16 , H01L2224/0401 , H01L2224/05599 , H01L2224/131 , H01L2224/16225 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/19015 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00
摘要： A structure includes a solder element for electrically coupling a substrate of an integrated circuit (IC) chip package and a printed circuit board (PCB); and a first electrical property altering, substantially planar member positioned between the solder element and at least one of a landing pad of the substrate and a landing pad of the PCB. In another embodiment, the electrical property altering, planar member can be applied to the solder element(s) between the IC chip and the package substrate.
摘要翻译：一种结构包括用于电耦合集成电路（IC）芯片封装的衬底和印刷电路板（PCB）的焊料元件; 以及位于所述焊料元件与所述基板的着陆焊盘和所述PCB的着陆焊盘中的至少一个之间的第一电性质改变的基本平坦的构件。在另一个实施例中，电性能改变的平面构件可以被施加到IC芯片和封装衬底之间的焊料元件。

5. 发明授权

US07759168B2 Electromagnetic interference shield for semiconductors using a continuous or near-continuous peripheral conducting seal and a conducting lid 失效
标题翻译：使用连续或近乎连续的外围导电密封和导电盖的半导体的电磁干扰屏蔽
公开(公告)号：US07759168B2
公开(公告)日：2010-07-20
申请号：US12119654
申请日：2008-05-13
申请人： J. Richard Behun , Erwin B. Cohen
发明人： J. Richard Behun , Erwin B. Cohen
IPC分类号： H01L21/52
CPC分类号： H01L23/552 , H01L23/04 , H01L23/10 , H01L24/16 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/16315 , H01L2924/166 , H01L2924/3025
摘要： A semiconductor package structure including a conductive adhesive material which is used to form an electromagnetic interference shield-forming Faraday cage. The Faraday cage incorporates a module lid as the top surface thereof, the conductive material as the sides and a laminate ground plane(s) or substrate as its bottom. Also disclosed is a method for fabricating the foregoing semiconductor package structure.
摘要翻译：一种半导体封装结构，包括用于形成电磁干扰屏蔽成形法拉第笼的导电粘合剂材料。法拉第笼包含模块盖作为其顶表面，导电材料作为侧面，并且层压接地平面或基底作为其底部。还公开了制造上述半导体封装结构的方法。

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