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1. 发明授权

US08058125B1 Poly resistor on a semiconductor device 有权
标题翻译：半导体器件上的聚电阻
公开(公告)号：US08058125B1
公开(公告)日：2011-11-15
申请号：US12850390
申请日：2010-08-04
申请人： Yu-Hsien Lin , Inez Fu , Yimin Huang
发明人： Yu-Hsien Lin , Inez Fu , Yimin Huang
IPC分类号： H01L21/8244
CPC分类号： H01L27/0629
摘要： The present disclosure provides a poly resistor on a semiconductor device and a method of fabricating the same. In an embodiment, a poly silicon resistor device is formed by providing a substrate having a first region and a second region. A dummy gate stack is formed on the substrate in the first region, wherein the dummy gate stack has a dummy gate stack thickness extending above the substrate. A poly silicon resister is formed on the substrate in the second region, wherein the poly silicon resistor has a poly silicon resistor thickness extending above the substrate a distance which is less than the dummy gate stack thickness. A dopant is implanted into the substrate in the first region thereby forming a source region and a drain region in the first region of the substrate. The dopant is also implanted into the poly silicon resistor. An inter-level dielectric (ILD) layer is formed on the substrate over the dummy gate stack and also over the poly silicon resistor. The ILD layer is planarized, thereby exposing the dummy gate stack and leaving a portion of the ILD layer over the poly silicon resistor. The dummy gate stack is replaced with a high k metal gate while using the portion of the ILD layer over the poly silicon resistor as a mask to protect the poly silicon resistor during replacement of the dummy gate stack with the high k metal gate.
摘要翻译：本公开在半导体器件上提供多晶硅电阻器及其制造方法。在一个实施例中，通过提供具有第一区域和第二区域的衬底来形成多晶硅电阻器件。在第一区域中的基板上形成虚拟栅极堆叠，其中虚拟栅极堆叠具有在基板上方延伸的虚拟栅极叠层厚度。在第二区域中的基板上形成多晶硅电阻器，其中多晶硅电阻器具有在基板上方延伸的距离小于虚拟栅极叠层厚度的多晶硅电阻器厚度。掺杂剂注入到第一区域中的衬底中，从而在衬底的第一区域中形成源极区域和漏极区域。掺杂剂也被注入到多晶硅电阻器中。在虚拟栅极堆叠上并且还在多晶硅电阻器上方的衬底上形成层间电介质（ILD）层。 ILD层被平坦化，从而暴露虚拟栅极堆叠并将ILD层的一部分留在多晶硅电阻上。在使用多晶硅电阻器上的ILD层的部分作为掩模的情况下，用高k金属栅极替代伪栅极堆叠，以在用高k金属栅极替换伪栅极堆叠期间保护多晶硅电阻器。

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