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1. 发明授权

US07645679B2 Method for forming isolation layer in semiconductor devices 失效
标题翻译：在半导体器件中形成隔离层的方法
公开(公告)号：US07645679B2
公开(公告)日：2010-01-12
申请号：US11612632
申请日：2006-12-19
申请人： In Kyu Chun
发明人： In Kyu Chun
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A method for forming an isolation layer for a semiconductor device is provided. The preferred method is capable of securing a gap fill margin during formation of an isolation layer. A device isolation layer formed according to a preferred method includes a trench formed in a device separation area of a semiconductor substrate; a thermal oxidation layer formed in a part of the trench; an oxidation silicon layer formed on the thermal oxidation layer; and an oxidation isolation layer formed on the oxidation silicon layer and filling the trench.
摘要翻译：提供一种用于形成半导体器件隔离层的方法。优选的方法能够在形成隔离层期间确保间隙填充余量。根据优选方法形成的器件隔离层包括形成在半导体衬底的器件分离区域中的沟槽; 形成在所述沟槽的一部分中的热氧化层; 形成在所述热氧化层上的氧化硅层; 以及形成在氧化硅层上并填充沟槽的氧化隔离层。

2. 发明申请

US20070161231A1 Method for forming metal wiring in a semiconductor device 审中-公开
标题翻译：在半导体器件中形成金属布线的方法
公开(公告)号：US20070161231A1
公开(公告)日：2007-07-12
申请号：US11646093
申请日：2006-12-26
申请人： In Kyu Chun
发明人： In Kyu Chun
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76885
摘要： Provided is a method for forming a metal wiring through a damascene process in a semiconductor device. The method includes: forming a metal diffusion barrier on a semiconductor substrate having a via hole and a trench therein; depositing a metal on the metal diffusion barrier, and filling the via hole and trench with the metal; performing a CMP process until an insulating layer is exposed, thereby forming the metal wiring from the metal; etching the exposed insulating layer by predetermined amount; and forming a passivation layer on the entire surface of the semiconductor substrate.
摘要翻译：提供一种通过半导体器件中的镶嵌工艺形成金属布线的方法。该方法包括：在其中具有通孔和沟槽的半导体衬底上形成金属扩散阻挡层; 在金属扩散阻挡层上沉积金属，并用金属填充通孔和沟槽; 进行CMP工序直到绝缘层露出，从而从金属形成金属布线; 蚀刻暴露的绝缘层预定量; 以及在半导体衬底的整个表面上形成钝化层。

3. 发明授权

US07482692B2 Tungsten plug structure of semiconductor device and method for forming the same 有权
标题翻译：半导体器件的钨插头结构及其形成方法
公开(公告)号：US07482692B2
公开(公告)日：2009-01-27
申请号：US11320698
申请日：2005-12-30
申请人： In Kyu Chun
发明人： In Kyu Chun
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A tungsten plug structure of a semiconductor device wherein a method for forming the same is performed at least twice to form a tungsten plug having a low aspect ratio, thereby obtaining an overlap margin between the tungsten plug and a metal line and minimizing contact resistance between the tungsten plug and a lower metal line layer. The plug structure of a semiconductor device includes a silicon substrate in which various elements for the semiconductor device are formed, a first dielectric film formed on the silicon substrate, having a first contact hole, a first plug buried in the first contact hole of the first dielectric film, having a low aspect ratio, a second dielectric film formed on an entire surface including the first dielectric film, having a second contact hole on the first plug, a second plug buried in the second contact hole of the second dielectric film, having a low aspect ratio, and a metal line formed on the second plug.
摘要翻译：一种半导体器件的钨插头结构，其中形成其形成方法至少两次以形成具有低纵横比的钨插塞，由此获得钨插头和金属线之间的重叠余量，并使接触电阻最小化钨丝塞和下金属线层。半导体器件的插头结构包括其中形成用于半导体器件的各种元件的硅衬底，形成在硅衬底上的第一电介质膜，具有第一接触孔，第一插头埋入第一接触孔具有低纵横比的介电膜，在包括第一电介质膜的整个表面上形成的第二电介质膜，在第一插塞上具有第二接触孔，埋在第二电介质膜的第二接触孔中的第二电极，具有低纵横比，以及形成在第二插头上的金属线。

4. 发明授权

US07271087B2 Dual damascene interconnection in semiconductor device and method for forming the same 有权
标题翻译：半导体器件中的双镶嵌互连及其形成方法
公开(公告)号：US07271087B2
公开(公告)日：2007-09-18
申请号：US11024657
申请日：2004-12-30
申请人： In-Kyu Chun
发明人： In-Kyu Chun
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76807 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A dual damascene interconnection in a semiconductor device is formed to be capable of preventing fluorine (F) component from being diffused through sidewalls of a via hole and a trench. The dual damascene interconnection includes a lower metal interconnection film, an intermetal insulating film having a via hole and a trench and formed on the lower metal interconnection film, first and second insulative spacer films formed on sidewalls of the via hole and the trench, respectively, a barrier metal layer covering the first and second insulative spacer films and the lower metal interconnection film in the via hole and the trench, and an upper metal interconnection film formed on the barrier metal layer, the via hole and the trench being filled with the upper metal interconnection film.
摘要翻译：半导体器件中的双镶嵌互连形成为能够防止氟（F）成分通过通孔和沟槽的侧壁扩散。双镶嵌互连包括下金属互连膜，具有通孔和沟槽并形成在下金属互连膜上的金属间绝缘膜，分别形成在通孔和沟槽的侧壁上的第一和第二绝缘隔离膜，覆盖通孔和沟槽中的第一和第二绝缘间隔膜和下金属互连膜的阻挡金属层和形成在阻挡金属层上的上金属互连膜，通孔和沟槽填充有上部金属互连膜。

5. 发明授权

US07238606B2 Semiconductor devices and method for fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07238606B2
公开(公告)日：2007-07-03
申请号：US11026941
申请日：2004-12-30
申请人： In Kyu Chun
发明人： In Kyu Chun
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/461
CPC分类号： H01L21/76849
摘要： Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating layer on a substrate having at least one predetermined structure, forms a trench and via hole through the first insulating layer by using a dual damascene process, and deposits a barrier layer along the bottom and the sidewalls of the trench and via hole. The example method forms a copper interconnect by filling the trench and via hole with copper and performing a planarization process, deposits a Ta/TaN layer over the substrate including the copper interconnect, removes some portion of the Ta/TaN layer so that the Ta/TaN layer remains only on the copper interconnect, deposits a second insulating layer over the substrate including the Ta/TaN layer, forms a via hole through the second insulating layer by removing some portion of the second insulating layer, and fills the via hole with a conductive material to complete a via.
摘要翻译：公开了制造半导体器件的铜互连的方法。用于制造半导体器件的铜互连的示例性方法在具有至少一个预定结构的衬底上沉积第一绝缘层，通过使用双镶嵌工艺形成通过第一绝缘层的沟槽和通孔，并且沉积阻挡层沿着沟槽和通孔的底部和侧壁。该示例方法通过用铜填充沟槽和通孔并执行平坦化工艺形成铜互连，在包括铜互连的衬底上沉积Ta / TaN层，去除Ta / TaN层的一部分，使得Ta / TaN层仅保留在铜互连上，在包括Ta / TaN层的衬底之上沉积第二绝缘层，通过去除第二绝缘层的一部分在第二绝缘层上形成通孔，并且用导电材料完成通孔。

6. 发明申请

US20050142803A1 Method for forming trench isolation in semiconductor device 审中-公开
标题翻译：在半导体器件中形成沟槽隔离的方法
公开(公告)号：US20050142803A1
公开(公告)日：2005-06-30
申请号：US11026915
申请日：2004-12-30
申请人： In-Kyu Chun
发明人： In-Kyu Chun
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/76237
摘要： Disclosed is a method for forming a trench device isolation film in a semiconductor device, which is capable of preventing voids from being generated, regardless of the trench aspect ratio. The method includes forming a trench in a device isolation field of a semiconductor substrate using a mask pattern on the semiconductor substrate, implanting oxygen in a lower portion of the trench, filling the trench with a fill insulating film, and stabilizing the implanted oxygen as an oxide film by annealing and/or compacting the fill insulating film.
摘要翻译：公开了一种在半导体器件中形成沟槽器件隔离膜的方法，其能够防止产生空隙，而与沟槽纵横比无关。该方法包括使用半导体衬底上的掩模图案在半导体衬底的器件隔离场中形成沟槽，在沟槽的下部注入氧，用填充绝缘膜填充沟槽，并将注入的氧稳定为氧化膜通过退火和/或压实填充绝缘膜。

7. 发明申请

US20070152335A1 Metal Interconnection of Semiconductor Device and Method for Forming the Same 失效
标题翻译：半导体器件的金属互连及其形成方法
公开(公告)号：US20070152335A1
公开(公告)日：2007-07-05
申请号：US11612638
申请日：2006-12-19
申请人： In Kyu Chun
发明人： In Kyu Chun
IPC分类号： H01L23/52
CPC分类号： H01L21/76834 , H01L21/76843 , H01L21/76885
摘要： Disclosed are a metal interconnection of a semiconductor device and a method for manufacturing the same, capable of improving the reliability of the semiconductor device. The metal interconnection of the semiconductor device includes a first metal interconnection formed on a semiconductor substrate; an interlayer dielectric layer formed on the semiconductor substrate including the first metal interconnection, the interlayer dielectric layer being selectively removed to form a via hole and a trench on the via hole; a metal diffusion blocking layer formed in the via hole and the trench formed on the via hole; a second metal interconnection buried in the via hole and the trench below a top portion of the metal diffusion blocking layer; and a protection layer covering the interlayer dielectric layer, the metal diffusion blocking layer, and the second metal interconnection.
摘要翻译：公开了半导体器件的金属互连及其制造方法，能够提高半导体器件的可靠性。半导体器件的金属互连包括形成在半导体衬底上的第一金属互连; 形成在包括第一金属互连的半导体衬底上的层间电介质层，选择性地去除层间绝缘层以在通孔上形成通孔和沟槽; 形成在通孔中的金属扩散阻挡层和形成在通孔上的沟槽; 掩埋在通孔中的第二金属互连和在金属扩散阻挡层的顶部下方的沟槽; 以及覆盖层间电介质层，金属扩散阻挡层和第二金属互连的保护层。

8. 发明授权

US07166532B2 Method for forming a contact using a dual damascene process in semiconductor fabrication 失效
标题翻译：在半导体制造中使用双镶嵌工艺形成接触的方法
公开(公告)号：US07166532B2
公开(公告)日：2007-01-23
申请号：US10712740
申请日：2003-11-13
申请人： In Kyu Chun
发明人： In Kyu Chun
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/76807 , H01L23/5226 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a contact using a Cu line in semiconductor fabrication process is disclosed. An example method forms a dual damascene pattern by etching a pre-metal dielectric (PMD) layer formed on a substrate. The dual damascene pattern includes a contact hole portion located on the substrate and a trench portion located on the contact hole portion. The width of the contact hole portion is narrower than that of the trench portion. The example method deposits a tungsten diffusion barrier on sidewalls of the damascene pattern, fills the damascene pattern with tungsten by depositing tungsten on the tungsten diffusion barrier to form a tungsten layer and uses chemical mechanical polishing to polish a portion of the tungsten layer over the trench portion. The example method also etches an upper part of the tungsten layer in the trench portion to form a tungsten plug that occupies a lower part of the tungsten layer in the trench portion and the contact hole portion, deposits a Cu diffusion barrier on the tungsten plug, and deposits a Cu on the Cu diffusion barrier.
摘要翻译：公开了一种在半导体制造工艺中使用Cu线形成接触的方法。示例性方法通过蚀刻形成在基底上的预金属电介质（PMD）层来形成双镶嵌图案。双镶嵌图案包括位于基板上的接触孔部分和位于接触孔部分上的沟槽部分。接触孔部的宽度比沟槽部的宽度窄。该示例性方法在大马士革图案的侧壁上沉积钨扩散阻挡层，通过在钨扩散屏障上沉积钨形成钨层并用钨填充镶嵌图案以形成钨层，并使用化学机械抛光来在该沟槽上抛光钨层的一部分一部分。该示例性方法还蚀刻沟槽部分中钨层的上部以形成占据沟槽部分和接触孔部分中的钨层的下部的钨插塞，在钨插塞上沉积Cu扩散阻挡层，并在Cu扩散屏障上沉积Cu。

9. 发明申请

US20070166949A1 Method for Forming Isolation Layer in Semiconductor Devices 失效
标题翻译：在半导体器件中形成隔离层的方法
公开(公告)号：US20070166949A1
公开(公告)日：2007-07-19
申请号：US11612632
申请日：2006-12-19
申请人： In Kyu Chun
发明人： In Kyu Chun
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A method for forming an isolation layer for a semiconductor device is provided. The preferred method is capable of securing a gap fill margin during formation of an isolation layer. A device isolation layer formed according to a preferred method includes a trench formed in a device separation area of a semiconductor substrate; a thermal oxidation layer formed in a part of the trench; an oxidation silicon layer formed on the thermal oxidation layer; and an oxidation isolation layer formed on the oxidation silicon layer and filling the trench.
摘要翻译：提供一种用于形成半导体器件隔离层的方法。优选的方法能够在形成隔离层期间确保间隙填充余量。根据优选方法形成的器件隔离层包括形成在半导体衬底的器件分离区域中的沟槽; 形成在所述沟槽的一部分中的热氧化层; 形成在所述热氧化层上的氧化硅层; 以及形成在氧化硅层上并填充沟槽的氧化隔离层。

10. 发明授权

US07763537B2 Metal interconnection of semiconductor device and method for forming the same 失效
标题翻译：半导体器件的金属互连及其形成方法
公开(公告)号：US07763537B2
公开(公告)日：2010-07-27
申请号：US11612638
申请日：2006-12-19
申请人： In Kyu Chun
发明人： In Kyu Chun
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76843 , H01L21/76885
摘要： Disclosed are a metal interconnection of a semiconductor device and a method for manufacturing the same, capable of improving the reliability of the semiconductor device. The metal interconnection of the semiconductor device includes a first metal interconnection formed on a semiconductor substrate; an interlayer dielectric layer formed on the semiconductor substrate including the first metal interconnection, the interlayer dielectric layer being selectively removed to form a via hole and a trench on the via hole; a metal diffusion blocking layer formed in the via hole and the trench formed on the via hole; a second metal interconnection buried in the via hole and the trench below a top portion of the metal diffusion blocking layer; and a protection layer covering the interlayer dielectric layer, the metal diffusion blocking layer, and the second metal interconnection.
摘要翻译：公开了半导体器件的金属互连及其制造方法，能够提高半导体器件的可靠性。半导体器件的金属互连包括形成在半导体衬底上的第一金属互连; 形成在包括第一金属互连的半导体衬底上的层间电介质层，选择性地去除层间绝缘层以在通孔上形成通孔和沟槽; 形成在通孔中的金属扩散阻挡层和形成在通孔上的沟槽; 掩埋在通孔中的第二金属互连和在金属扩散阻挡层的顶部下方的沟槽; 以及覆盖层间电介质层，金属扩散阻挡层和第二金属互连的保护层。

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