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1. 发明申请

US20060081765A1 Semiconductor integrated circuit device having a plurality of photo detectors and processing elements 失效
公开(公告)号：US20060081765A1
公开(公告)日：2006-04-20
申请号：US11289696
申请日：2005-11-30
申请人： Masatoshi Ishikawa , Idaku Ishii , Takashi Komuro , Shingo Kagami
发明人： Masatoshi Ishikawa , Idaku Ishii , Takashi Komuro , Shingo Kagami
IPC分类号： H01L27/00
CPC分类号： G01J1/4228 , G01J1/0204 , H04N5/335
摘要： A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.

2. 发明授权

US07244919B2 Semiconductor integrated circuit device having photo detector circuits, processing elements, and comparing circuits which compare the output of a photo detector element with a reference voltage 失效
标题翻译：具有光检测器电路，处理元件和比较电路的半导体集成电路器件，其比较光检测器元件的输出与参考电压
公开(公告)号：US07244919B2
公开(公告)日：2007-07-17
申请号：US11289696
申请日：2005-11-30
申请人： Masatoshi Ishikawa , Idaku Ishii , Takashi Komuro , Shingo Kagami
发明人： Masatoshi Ishikawa , Idaku Ishii , Takashi Komuro , Shingo Kagami
IPC分类号： H01L27/00
CPC分类号： G01J1/4228 , G01J1/0204 , H04N5/335
摘要： A semiconductor integrated circuit device is provided which has a plurality of photo detector circuits and a plurality of processing elements. Each of the photo detector circuits includes a comparing circuit, which compares an output of a photo detector element with a reference voltage. A/D conversion is performed by counting the elapsed time until the output of the photo detector element drops below the reference voltage, and a level of the reference voltage as a function of time to be applied to the comparing circuit and time intervals of the counting are uniquely determined based on given quantization intervals of an amount of current generated by the photo detector element. In addition, the photo detector elements may be reset locally based on the result of the corresponding processing element.
摘要翻译：提供一种具有多个光电检测器电路和多个处理元件的半导体集成电路器件。每个光检测器电路包括比较电路，其比较光检测器元件的输出与参考电压。通过计算直到光电检测器元件的输出低于参考电压的经过时间，以及作为施加到比较电路的时间的参考电压的电平和计数的时间间隔来执行A / D转换基于由光电检测器元件产生的电流量的给定量化间隔唯一确定。此外，可以基于对应的处理元件的结果来本地复位光电检测器元件。

3. 发明授权

US07046821B2 Image detection processor 有权
标题翻译：图像检测处理器
公开(公告)号：US07046821B2
公开(公告)日：2006-05-16
申请号：US09760331
申请日：2001-01-13
申请人： Masatoshi Ishikawa , Idaku Ishii , Takashi Komuro , Yoshihiro Nakabo , Atsushi Yoshida
发明人： Masatoshi Ishikawa , Idaku Ishii , Takashi Komuro , Yoshihiro Nakabo , Atsushi Yoshida
IPC分类号： G06K9/00
CPC分类号： G06T1/20
摘要： An image detection processor of the present invention enhances the processing speed of the calculation of the center of gravity or the like of a target with a simple constitution. The image detection processor arranges a plurality of image detection processing elements 1-1 to 1-64 on a plane. Each image detection processing element includes an adder circuit 15 which converts an output of a photoelectric conversion part 5 into digital signals and can receive the digital signals as an input in a matrix form. Cumulative adders are constituted by connecting the adder circuits 15 for respective rows. Series adders 2-1 to 2-8 which are connected in series respectively receive outputs of final stages of cumulative adders of respective rows as inputs and can cumulatively add these outputs. The digital signals are selectively inputted to the cumulative adders using a row decoder 3 and a column decoder 4 and processed data of an image detected by photoelectric conversion parts 5 of a plurality of image detection processing elements are outputted from the series adder 2-8. Due to such a constitution, the processed data necessary for an image processing such as the calculation of the center of gravity can be produced at the time of transferring data thus realizing rapid processing.
摘要翻译：本发明的图像检测处理器以简单的结构提高了目标的重心等的计算处理速度。图像检测处理器在平面上布置多个图像检测处理元件1-1至1〜64。每个图像检测处理元件包括加法器电路15，其将光电转换部分5的输出转换成数字信号，并且可以以矩阵形式接收数字信号作为输入。累积加法器通过连接各行的加法器电路15构成。串联连接的串联加法器2 - 1 - 2 - 8分别接收相应行累积加法器的最终级的输出作为输入，并且可以累加地添加这些输出。使用行解码器3和列解码器4将数字信号选择性地输入到累积加法器，并且从串联加法器2-8输出由多个图像检测处理元件的光电转换部分5检测的图像的处理数据。由于这样的结构，可以在传送数据时产生诸如计算重心的图像处理所需的处理数据，从而实现快速处理。

4. 发明申请

US20060081767A1 Semiconductor integrated circuit device having a plurality of photo detectors and processing elements 失效
公开(公告)号：US20060081767A1
公开(公告)日：2006-04-20
申请号：US11289695
申请日：2005-11-30
申请人： Masatoshi Ishikawa , Idaku Ishii , Takashi Komuro , Shingo Kagami
发明人： Masatoshi Ishikawa , Idaku Ishii , Takashi Komuro , Shingo Kagami
IPC分类号： G01J1/42
CPC分类号： G01J1/4228 , G01J1/0204 , H04N5/335
摘要： A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.

5. 发明授权

US08244788B2 Semiconductor integrated circuit device having a plurality of photo detectors and processing elements 失效
标题翻译：具有多个光电检测器和处理元件的半导体集成电路器件
公开(公告)号：US08244788B2
公开(公告)日：2012-08-14
申请号：US11289695
申请日：2005-11-30
申请人： Masatoshi Ishikawa , Idaku Ishii , Takashi Komuro , Shingo Kagami
发明人： Masatoshi Ishikawa , Idaku Ishii , Takashi Komuro , Shingo Kagami
IPC分类号： G06F7/38
CPC分类号： G01J1/4228 , G01J1/0204 , H04N5/335
摘要： A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.
摘要翻译：具有容纳在单个半导体芯片上的多个处理元件的半导体集成电路器件具有锁存电路和选择电路。锁存电路设置在每个处理元件的输出处。选择电路从由上，下，左，右处理元件组成的组和零信号中选择输入源。

6. 发明授权

US07098437B2 Semiconductor integrated circuit device having a plurality of photo detectors and processing elements 失效
公开(公告)号：US07098437B2
公开(公告)日：2006-08-29
申请号：US10200332
申请日：2002-07-23
申请人： Masatoshi Ishikawa , Idaku Ishii , Takashi Komuro , Shingo Kagami
发明人： Masatoshi Ishikawa , Idaku Ishii , Takashi Komuro , Shingo Kagami
IPC分类号： G01J1/42
CPC分类号： G01J1/4228 , G01J1/0204 , H04N5/335
摘要： A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.

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