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1. 发明授权

US09495290B2 Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering 有权
标题翻译：各种方法和设备，以支持对多个目标的未完成请求，同时保持事务顺序
公开(公告)号：US09495290B2
公开(公告)日：2016-11-15
申请号：US12144987
申请日：2008-06-24
申请人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
发明人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
IPC分类号： G06F9/46 , G06F9/455 , G06F12/06 , G06F15/173
CPC分类号： G11C7/1072 , G06F12/0607 , G06F15/17375 , Y02D10/13
摘要： A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.
摘要翻译：描述了一种方法，装置和系统，其通常涉及具有实现内部控制的互连的集成电路。集成电路中的互连通信发起者知识产权（IP）核心和耦合到互连的目标IP核之间的交易。互连实现逻辑，其被配置为支持从第一发起方IP核向多个目标IP核发出的多个事务，同时维持事务内的预期执行顺序。在从相同的第一起始IP核发送到第一目标IP核的第一事务完成之前，该逻辑支持将从第一发起者IP核发送到第二目标IP核的第二事务，同时确保第一事务完成之前同时确保在第一事务和第二事务期间的预期执行顺序。该逻辑不包括任何重新排序缓冲。

2. 发明授权

US08024697B2 Various methods and apparatuses for estimating characteristics of an electronic systems design 有权
标题翻译：用于估计电子系统设计特性的各种方法和装置
公开(公告)号：US08024697B2
公开(公告)日：2011-09-20
申请号：US12729509
申请日：2010-03-23
申请人： Stephen Hamilton , Ian Andrew Swarbrick , Scott Carlton Evans , Wolf-Dietrich Weber , Jay S. Tomlinson
发明人： Stephen Hamilton , Ian Andrew Swarbrick , Scott Carlton Evans , Wolf-Dietrich Weber , Jay S. Tomlinson
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： G06F17/5045 , G06F17/50 , G06F2217/78 , G06F2217/84
摘要： Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.
摘要翻译：描述了用于估计电子系统设计的时间，面积和功率特性的知识产权（IP）发生器的方法和装置。 IP生成器接收用户提供的文件，该文件具有描述具有多层次结构的IP设计的配置的数据。 IP生成器还接收用户提供的技术参数和数据流信息。 IP生成器根据用户提供的技术参数，数据流信息和配置参数，关联每个IP子组件的估计时序，面积和功率特性。在将寄存器传输级别（RTL）设计转换为门级电路设计之前，IP生成器通过图形用户界面向用户报告定时，面积和功率估计。

3. 发明申请

US20080320476A1 VARIOUS METHODS AND APPARATUS TO SUPPORT OUTSTANDING REQUESTS TO MULTIPLE TARGETS WHILE MAINTAINING TRANSACTION ORDERING 有权
标题翻译：支持在维护交易订单时支持多项目标要求的各种方法和设备
公开(公告)号：US20080320476A1
公开(公告)日：2008-12-25
申请号：US12144987
申请日：2008-06-24
申请人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
发明人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
IPC分类号： G06F9/46
CPC分类号： G11C7/1072 , G06F12/0607 , G06F15/17375 , Y02D10/13
摘要： A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.
摘要翻译：描述了一种方法，装置和系统，其通常涉及具有实现内部控制的互连的集成电路。集成电路中的互连通信发起者知识产权（IP）核心和耦合到互连的目标IP核之间的交易。互连实现逻辑，其被配置为支持从第一发起方IP核向多个目标IP核发出的多个事务，同时维持事务内的预期执行顺序。在从相同的第一起始IP核发送到第一目标IP核的第一事务完成之前，该逻辑支持将从第一发起者IP核发送到第二目标IP核的第二事务，同时确保第一事务完成之前同时确保在第一事务和第二事务期间的预期执行顺序。该逻辑不包括任何重新排序缓冲。

4. 发明授权

US07149829B2 Various methods and apparatuses for arbitration among blocks of functionality 有权
标题翻译：用于在功能块之间进行仲裁的各种方法和装置
公开(公告)号：US07149829B2
公开(公告)日：2006-12-12
申请号：US10418370
申请日：2003-04-18
申请人： Wolf-Dietrich Weber , Ian Andrew Swarbrick , Jay S. Tomlinson
发明人： Wolf-Dietrich Weber , Ian Andrew Swarbrick , Jay S. Tomlinson
IPC分类号： G06F12/00
CPC分类号： G06F13/364 , G06F9/526 , G06F2209/522
摘要： Various methods and apparatuses are described in which an arbitration controller cooperates with arbitration logic. The arbitration controller has a plurality of inputs that receive one or more transactions from a plurality of blocks of functionality. The arbitration controller arbitrates requests for access to a shared resource amongst the plurality of blocks of functionality by implementing an arbitration policy. The arbitration policy groups the transactions from the plurality of blocks of functionality into global groups of transactions for servicing by that shared resource. All of the transactions in a first global group are serviced by that shared resource prior to servicing transactions in a next global group of transactions. The arbitration logic facilitates the arbitration policy. The arbitration logic includes cascaded arbitration units that hierarchically arbitrate for the shared resource. The topology of the functional blocks supplying the transactions to the inputs into the arbitration controller is capable of varying independently of the arbitration policy achieved by the collection of arbitration units.
摘要翻译：描述了各种方法和装置，其中仲裁控制器与仲裁逻辑协作。仲裁控制器具有从多个功能块接收一个或多个事务的多个输入。仲裁控制器通过实施仲裁政策来仲裁多个功能块之间对共享资源的访问请求。仲裁策略将来自多个功能块的交易分组为全局交易组，以供该共享资源进行服务。第一个全球组中的所有交易在该下一个全球交易组中为交易提供服务之前由该共享资源提供服务。仲裁逻辑有助于仲裁政策。仲裁逻辑包括级联仲裁用于共享资源的级联仲裁单元。将交易提供给仲裁控制器的输入的功能块的拓扑能够独立于通过收集仲裁单元实现的仲裁策略而变化。

5. 发明申请

US20100318946A1 VARIOUS METHODS AND APPARATUSES FOR ESTIMATING CHARACTERISTICS OF AN ELECTRONIC SYSTEMS DESIGN 有权
标题翻译：用于估计电子系统设计特性的各种方法和装置
公开(公告)号：US20100318946A1
公开(公告)日：2010-12-16
申请号：US12729509
申请日：2010-03-23
申请人： Stephen Hamilton , Ian Andrew Swarbrick , Scott Carlton Evans , Wolf-Dietrich Weber , Jay S. Tomlinson
发明人： Stephen Hamilton , Ian Andrew Swarbrick , Scott Carlton Evans , Wolf-Dietrich Weber , Jay S. Tomlinson
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/50 , G06F2217/78 , G06F2217/84
摘要： Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.
摘要翻译：描述了用于估计电子系统设计的时间，面积和功率特性的知识产权（IP）发生器的方法和装置。 IP生成器接收用户提供的文件，该文件具有描述具有多层次结构的IP设计的配置的数据。 IP生成器还接收用户提供的技术参数和数据流信息。 IP生成器根据用户提供的技术参数，数据流信息和配置参数，关联每个IP子组件的估计时序，面积和功率特性。在将寄存器传输级别（RTL）设计转换为门级电路设计之前，IP生成器通过图形用户界面向用户报告定时，面积和功率估计。

6. 发明授权

US09292436B2 Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary 有权
标题翻译：用于支持该事务中的数据地址序列跨越交织的信道地址边界的事务的各种方法和装置
公开(公告)号：US09292436B2
公开(公告)日：2016-03-22
申请号：US12145052
申请日：2008-06-24
申请人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
发明人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
IPC分类号： G06F12/06 , G06F15/173
CPC分类号： G11C7/1072 , G06F12/0607 , G06F15/17375 , Y02D10/13
摘要： A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.
摘要翻译：描述了一种方法，装置和系统，其通常涉及到目标IP核的互连路由事务，包括构成第一聚合目标的两个或更多个信道。两个或更多个通道填充分配给第一个聚合目标的地址空间，并显示为发起者IP内核的单个目标。互连实现斩波逻辑，以将来自第一起始IP的核心的单个事务从第一发起者IP核中切出，该第一发起者IP核的地址序列跨越第一信道的信道地址边界到第一聚合目标内的第二信道，成为两个或多个突发事务。第一切碎突发事务被切碎以适合第一通道的地址边界内，并且第二切断突发事务被切碎以适合于第二通道的地址边界内。

7. 发明授权

US07694249B2 Various methods and apparatuses for estimating characteristics of an electronic system's design 有权
标题翻译：用于估计电子系统设计特征的各种方法和装置
公开(公告)号：US07694249B2
公开(公告)日：2010-04-06
申请号：US11398036
申请日：2006-04-04
申请人： Stephen Hamilton , Ian Andrew Swarbrick , Scott Carlton Evans , Wolf-Dietrich Weber , Jay S. Tomlinson
发明人： Stephen Hamilton , Ian Andrew Swarbrick , Scott Carlton Evans , Wolf-Dietrich Weber , Jay S. Tomlinson
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045 , G06F17/50 , G06F2217/78 , G06F2217/84
摘要： Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.
摘要翻译：描述了用于估计电子系统设计的时间，面积和功率特性的知识产权（IP）发生器的方法和装置。 IP生成器接收用户提供的文件，该文件具有描述具有多层次结构的IP设计的配置的数据。 IP生成器还接收用户提供的技术参数和数据流信息。 IP生成器根据用户提供的技术参数，数据流信息和配置参数，关联每个IP子组件的估计时序，面积和功率特性。在将寄存器传输级别（RTL）设计转换为门级电路设计之前，IP生成器通过图形用户界面向用户报告定时，面积和功率估计。

8. 发明申请

US20080320268A1 INTERCONNECT IMPLEMENTING INTERNAL CONTROLS 有权
标题翻译：互连实现内部控制
公开(公告)号：US20080320268A1
公开(公告)日：2008-12-25
申请号：US12144883
申请日：2008-06-24
申请人： Drew E. Wingard , Chien-Chun Chou , Ian Andrew Swarbrick , Stephen W. Hamilton , Vida Vakilotojar
发明人： Drew E. Wingard , Chien-Chun Chou , Ian Andrew Swarbrick , Stephen W. Hamilton , Vida Vakilotojar
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G11C7/1072 , G06F12/0607 , G06F15/17375 , Y02D10/13
摘要： In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.
摘要翻译：在一个实施例中，用于集成电路的互连传送一个或多个启动器知识产权（IP）核与耦合到互连的多个目标IP核之间的事务。两个或多个内存通道组成目标IP内核的第一个聚合目标。两个或多个内存通道填充分配给第一个聚合目标的地址空间，并显示为发起者IP内核的单个目标。互连实现斩波逻辑以将从第一存储器通道的存储器通道地址边界跨越第一聚合目标内的第二存储器通道的单独的二维（2D）事务转换为具有大于1的高度值的两个或更多个2D事务，以及步长和宽度尺寸，其被切碎以适合于第一聚集目标的存储器通道地址边界。

9. 发明申请

US20080320254A1 VARIOUS METHODS AND APPARATUS TO SUPPORT TRANSACTIONS WHOSE DATA ADDRESS SEQUENCE WITHIN THAT TRANSACTION CROSSES AN INTERLEAVED CHANNEL ADDRESS BOUNDARY 有权
标题翻译：各种方法和设备支持交易之间的数据地址顺序交叉交叉通道地址边界
公开(公告)号：US20080320254A1
公开(公告)日：2008-12-25
申请号：US12145052
申请日：2008-06-24
申请人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
发明人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
IPC分类号： G06F12/06
CPC分类号： G11C7/1072 , G06F12/0607 , G06F15/17375 , Y02D10/13
摘要： A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.
摘要翻译：描述了一种方法，装置和系统，其通常涉及到目标IP核的互连路由事务，包括构成第一聚合目标的两个或更多个信道。两个或更多个通道填充分配给第一个聚合目标的地址空间，并显示为发起者IP内核的单个目标。互连实现斩波逻辑，以将来自第一起始IP的核心的单个事务从第一发起者IP核中切出，该第一发起者IP核的地址序列跨越第一信道的信道地址边界到第一聚合目标内的第二信道，成为两个或多个突发事务。第一切碎突发事务被切碎以适合第一通道的地址边界内，并且第二切断突发事务被切碎以适合于第二通道的地址边界内。

10. 发明授权

US08407433B2 Interconnect implementing internal controls 有权
标题翻译：互连实现内部控制
公开(公告)号：US08407433B2
公开(公告)日：2013-03-26
申请号：US12144883
申请日：2008-06-24
申请人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
发明人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
IPC分类号： G06F12/00
CPC分类号： G11C7/1072 , G06F12/0607 , G06F15/17375 , Y02D10/13
摘要： In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.
摘要翻译：在一个实施例中，用于集成电路的互连传送一个或多个启动器知识产权（IP）核与耦合到互连的多个目标IP核之间的事务。两个或多个内存通道组成目标IP内核的第一个聚合目标。两个或多个内存通道填充分配给第一个聚合目标的地址空间，并显示为发起者IP内核的单个目标。互连实现斩波逻辑以将从第一存储器通道的存储器通道地址边界跨越第一聚合目标内的第二存储器通道的单独的二维（2D）事务转换为具有大于1的高度值的两个或更多个2D事务，以及步长和宽度尺寸，其被切碎以适合于第一聚集目标的存储器通道地址边界。

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