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1. 发明授权

US08659033B2 Light-emitting diode with textured substrate 有权
标题翻译：具纹理衬底的发光二极管
公开(公告)号：US08659033B2
公开(公告)日：2014-02-25
申请号：US13267701
申请日：2011-10-06
申请人： Chen-Hua Yu , Wen-Chih Chiou , Ding-Yuan Chen , Chia-Lin Yu , Hung-Ta Lin
发明人： Chen-Hua Yu , Wen-Chih Chiou , Ding-Yuan Chen , Chia-Lin Yu , Hung-Ta Lin
IPC分类号： H01L27/15 , H01L29/26 , H01L31/12 , H01L33/00
CPC分类号： H01L33/22 , H01L33/007 , H01L33/0075 , H01L33/06 , H01L33/24 , H01L33/32
摘要： A light-emitting diode (LED) device is provided. The LED device has raised semiconductor regions formed on a substrate. LED structures are formed over the raised semiconductor regions such that bottom contact layers and active layers of the LED device are conformal layers. The top contact layer has a planar surface. In an embodiment, the top contact layers are continuous over a plurality of the raised semiconductor regions while the bottom contact layers and the active layers are discontinuous between adjacent raised semiconductor regions.
摘要翻译：提供了一种发光二极管（LED）装置。 LED装置已经凸起形成在基板上的半导体区域。在凸起的半导体区域上形成LED结构，使得LED器件的底部接触层和有源层是保形层。顶部接触层具有平坦的表面。在一个实施例中，顶部接触层在多个凸起的半导体区域上是连续的，而底部接触层和有源层在相邻凸起的半导体区域之间是不连续的。

2. 发明申请

US20130099243A1 SUBSTRATE BREAKDOWN VOLTAGE IMPROVEMENT FOR GROUP III-NITRIDE ON A SILICON SUBSTRATE 有权
标题翻译：硅基底板上III组氮化物的基板突变电压改进
公开(公告)号：US20130099243A1
公开(公告)日：2013-04-25
申请号：US13277692
申请日：2011-10-20
申请人： Chi-Ming CHEN , Po-Chun LIU , Hung-Ta LIN , Chin-Cheng CHANG , Chung-Yi YU , Chia-Shiung TSAI , Ho-Yung David HWANG
发明人： Chi-Ming CHEN , Po-Chun LIU , Hung-Ta LIN , Chin-Cheng CHANG , Chung-Yi YU , Chia-Shiung TSAI , Ho-Yung David HWANG
IPC分类号： H01L29/20 , H01L21/20
CPC分类号： H01L21/02381 , H01L21/02458 , H01L21/02505 , H01L21/0251 , H01L21/0254 , H01L21/02579 , H01L21/0262 , H01L29/2003 , H01L29/41766 , H01L29/452 , H01L29/517 , H01L29/66462 , H01L29/7787
摘要： A circuit structure includes a substrate, a nucleation layer of undoped aluminum nitride, a graded buffer layer comprising aluminum, gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant, a ungraded buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant without aluminum, and a bulk layer of undoped gallium nitride over the ungraded buffer layer. The various dopants in the graded buffer layer and the ungraded buffer layer increases resistivity and results in layers having an intrinsically balanced conductivity.
摘要翻译：电路结构包括衬底，未掺杂的氮化铝的成核层，包含铝，镓，氮，硅和氧中的一种的梯度缓冲层和p型导电掺杂剂，包含镓，氮，一个的硅和氧，以及没有铝的p型导电掺杂物，以及未分级缓冲层上的未掺杂氮化镓的体层。分级缓冲层和未分级缓冲层中的各种掺杂剂增加了电阻率并导致具有本质上平衡的导电性的层。

3. 发明申请

US20130095642A1 JUNCTION LEAKAGE REDUCTION THROUGH IMPLANTATION 有权
标题翻译：通过植入减少接头泄漏
公开(公告)号：US20130095642A1
公开(公告)日：2013-04-18
申请号：US13273463
申请日：2011-10-14
申请人： Chun-Feng Nieh , Chung-Yi Yu , Hung-Ta Lin
发明人： Chun-Feng Nieh , Chung-Yi Yu , Hung-Ta Lin
IPC分类号： H01L21/20
CPC分类号： H01L29/66522 , H01L21/2654 , H01L29/267
摘要： Provided is a method of fabricating a semiconductor device. The method includes forming a first III-V family layer over a substrate. The first III-V family layer includes a surface having a first surface morphology. The method includes performing an ion implantation process to the first III-V family layer through the surface. The ion implantation process changes the first surface morphology into a second surface morphology. After the ion implantation process is performed, the method includes forming a second III-V family layer over the first III-V family layer. The second III-V family layer has a material composition different from that of the first III-V family layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在衬底上形成第一III-V族层。第一III-V族层包括具有第一表面形态的表面。该方法包括通过表面对第一III-V族层执行离子注入工艺。离子注入工艺将第一表面形态变为第二表面形态。在执行离子注入工艺之后，该方法包括在第一III-V族层上形成第二III-V族层。第二III-V族层具有不同于第一III-V族层的材料成分。

4. 发明申请

US20120119236A1 Light-Emitting Diodes on Concave Texture Substrate 有权
标题翻译：凹面纹理基板上的发光二极管
公开(公告)号：US20120119236A1
公开(公告)日：2012-05-17
申请号：US13358327
申请日：2012-01-25
申请人： Chen-Hua Yu , Hung-Ta Lin , Wen-Chih Chiou , Ding-Yuan Chen , Chia-Lin Yu
发明人： Chen-Hua Yu , Hung-Ta Lin , Wen-Chih Chiou , Ding-Yuan Chen , Chia-Lin Yu
IPC分类号： H01L27/15 , H01L33/48
CPC分类号： H01L33/48 , H01L33/20 , H01L33/24
摘要： A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency.
摘要翻译：提供了一种形成在凹面纹理基板上的发光二极管（LED）的半导体器件。对衬底进行图案化和蚀刻以形成凹陷。沿着凹部的底部形成分离层。沿着侧壁和任选地沿着相邻凹部之间的基板的表面形成LED结构。在这些实施例中，与平面表面相比，LED结构的表面积增加。在另一个实施例中，LED结构形成在凹部内，使得底部接触层与凹部的拓扑不一致。在这些实施例中，硅衬底中的凹陷导致底接触层中的立方结构，例如具有非极性特性并且表现出更高外部量子效率的n-GaN层。

5. 发明授权

US08058082B2 Light-emitting diode with textured substrate 有权
标题翻译：具纹理衬底的发光二极管
公开(公告)号：US08058082B2
公开(公告)日：2011-11-15
申请号：US12189635
申请日：2008-08-11
申请人： Chen-Hua Yu , Wen-Chih Chiou , Ding-Yuan Chen , Chia-Lin Yu , Hung-Ta Lin
发明人： Chen-Hua Yu , Wen-Chih Chiou , Ding-Yuan Chen , Chia-Lin Yu , Hung-Ta Lin
IPC分类号： H01L21/00
CPC分类号： H01L33/22 , H01L33/007 , H01L33/0075 , H01L33/06 , H01L33/24 , H01L33/32
摘要： A light-emitting diode (LED) device is provided. The LED device has raised semiconductor regions formed on a substrate. LED structures are formed over the raised semiconductor regions such that bottom contact layers and active layers of the LED device are conformal layers. The top contact layer has a planar surface. In an embodiment, the top contact layers are continuous over a plurality of the raised semiconductor regions while the bottom contact layers and the active layers are discontinuous between adjacent raised semiconductor regions.
摘要翻译：提供了一种发光二极管（LED）装置。 LED装置已经凸起形成在基板上的半导体区域。在凸起的半导体区域上形成LED结构，使得LED器件的底部接触层和有源层是保形层。顶部接触层具有平坦的表面。在一个实施例中，顶部接触层在多个凸起的半导体区域上是连续的，而底部接触层和有源层在相邻凸起的半导体区域之间是不连续的。

6. 发明申请

US20100051965A1 Carbon-Containing Semiconductor Substrate 有权
标题翻译：含碳半导体基板
公开(公告)号：US20100051965A1
公开(公告)日：2010-03-04
申请号：US12509339
申请日：2009-07-24
申请人： Chen-Hua Yu , Chia-Lin Yu , Ding-Yuan Chen , Wen-Chih Chiou , Hung-Ta Lin
发明人： Chen-Hua Yu , Chia-Lin Yu , Ding-Yuan Chen , Wen-Chih Chiou , Hung-Ta Lin
IPC分类号： H01L33/00
CPC分类号： H01L33/007 , H01L21/02381 , H01L21/02447 , H01L21/02458 , H01L21/02491 , H01L21/02505 , H01L21/0254 , H01L21/223 , H01L21/26506 , H01L33/025
摘要： A light-emitting diode (LED) device is provided. The LED device is formed on a substrate having a carbon-containing layer. Carbon atoms are introduced into the substrate to prevent or reduce atoms from an overlying metal/metal alloy transition layer from inter-mixing with atoms of the substrate. In this manner, a crystalline structure is maintained upon which the LED structure may be formed.
摘要翻译：提供了一种发光二极管（LED）装置。 LED装置形成在具有含碳层的基板上。将碳原子引入衬底中以防止或减少来自上层金属/金属合金过渡层的原子与衬底的原子的混合。以这种方式，保持可以形成LED结构的晶体结构。

7. 发明授权

US08629465B2 Light-emitting diodes on concave texture substrate 有权
标题翻译：凹面纹理基板上的发光二极管
公开(公告)号：US08629465B2
公开(公告)日：2014-01-14
申请号：US13358327
申请日：2012-01-25
申请人： Chen-Hua Yu , Hung-Ta Lin , Wen-Chih Chiou , Ding-Yuan Chen , Chia-Lin Yu
发明人： Chen-Hua Yu , Hung-Ta Lin , Wen-Chih Chiou , Ding-Yuan Chen , Chia-Lin Yu
IPC分类号： H01L33/08
CPC分类号： H01L33/48 , H01L33/20 , H01L33/24
摘要： A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency.
摘要翻译：提供了一种形成在凹面纹理基板上的发光二极管（LED）的半导体器件。对衬底进行图案化和蚀刻以形成凹陷。沿着凹部的底部形成分离层。沿着侧壁和任选地沿着相邻凹部之间的基板的表面形成LED结构。在这些实施例中，与平面表面相比，LED结构的表面积增加。在另一个实施例中，LED结构形成在凹部内，使得底部接触层与凹部的拓扑不一致。在这些实施例中，硅衬底中的凹槽导致底接触层中的立方结构，例如具有非极性特性并且表现出更高外部量子效率的n-GaN层。

8. 发明授权

US08629037B2 Forming a protective film on a back side of a silicon wafer in a III-V family fabrication process 有权
标题翻译：在III-V族制造工艺中在硅晶片的背面形成保护膜
公开(公告)号：US08629037B2
公开(公告)日：2014-01-14
申请号：US13244340
申请日：2011-09-24
申请人： Chun-Feng Nieh , Chung-Yi Yu , Hung-Ta Lin
发明人： Chun-Feng Nieh , Chung-Yi Yu , Hung-Ta Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided is a method of fabricating a semiconductor device. The method includes forming a first dielectric layer over a first surface and a second surface of a silicon substrate. the first and second surfaces being opposite surfaces. A first portion of the first dielectric layer covers the first surface of the substrate, and a second portion of the first dielectric layer covers the second surface of the substrate. The method includes forming openings that extend into the substrate from the first surface. The method includes filling the openings with a second dielectric layer. The method includes removing the first portion of the first dielectric layer without removing the second portion of the first dielectric layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在硅衬底的第一表面和第二表面上形成第一电介质层。第一和第二表面是相对的表面。第一介电层的第一部分覆盖基板的第一表面，并且第一介电层的第二部分覆盖基板的第二表面。该方法包括形成从第一表面延伸到基底中的开口。该方法包括用第二介电层填充开口。该方法包括在不去除第一介电层的第二部分的情况下去除第一介电层的第一部分。

9. 发明授权

US08440517B2 FinFET and method of fabricating the same 有权
标题翻译： FinFET及其制造方法
公开(公告)号：US08440517B2
公开(公告)日：2013-05-14
申请号：US12903712
申请日：2010-10-13
申请人： Hung-Ta Lin , Chu-Yun Fu , Shin-Yeh Huang , Shu-Tine Yang , Hung-Ming Chen
发明人： Hung-Ta Lin , Chu-Yun Fu , Shin-Yeh Huang , Shu-Tine Yang , Hung-Ming Chen
IPC分类号： H01L21/02
CPC分类号： H01L27/0886 , H01L21/02293 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7842 , H01L29/7848 , H01L29/785 , H01L29/7855
摘要： The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces; a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin comprises a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin comprises a non-recessed portion having a top surface higher than the tapered top surfaces; and a gate stack over the non-recessed portion of the fin.
摘要翻译：本发明涉及鳍状场效应晶体管（FinFET）。 FinFET的示例性结构包括：包括顶表面的衬底; 第一绝缘区域和位于衬底顶表面上的第二绝缘区域，包括锥形顶表面; 在所述第一和第二绝缘区域之间延伸到所述衬底顶表面之上的所述衬底的翅片，其中所述鳍片包括具有比所述第一和第二绝缘区域的锥形顶表面低的顶表面的凹陷部分，其中所述鳍片包括非加工部分具有高于锥形顶表面的顶表面; 以及在翅片的非凹陷部分上方的栅极堆叠。

10. 发明申请

US20130099283A1 III-V Multi-Channel FinFETs 有权
公开(公告)号：US20130099283A1
公开(公告)日：2013-04-25
申请号：US13278601
申请日：2011-10-21
申请人： Hung-Ta Lin , Chun-Feng Nieh , Chung-Yi Yu , Chi-Ming Chen
发明人： Hung-Ta Lin , Chun-Feng Nieh , Chung-Yi Yu , Chi-Ming Chen
IPC分类号： H01L29/205 , H01L21/20
CPC分类号： H01L29/267 , H01L21/02546 , H01L21/30612 , H01L21/76224 , H01L29/0653 , H01L29/155 , H01L29/205 , H01L29/66462 , H01L29/66522 , H01L29/66795 , H01L29/7783 , H01L29/785
摘要： A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.

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