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1. 发明授权

US06974736B2 Method of forming FET silicide gate structures incorporating inner spacers 失效
标题翻译：形成内置衬垫的FET硅化物栅极结构的方法
公开(公告)号：US06974736B2
公开(公告)日：2005-12-13
申请号：US10707759
申请日：2004-01-09
申请人： Victor Ku , An Steegen , Hsing-Jen C. Wann , Keith Kwong Hon Wong
发明人： Victor Ku , An Steegen , Hsing-Jen C. Wann , Keith Kwong Hon Wong
IPC分类号： H01L21/335 , H01L21/04 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/28194 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/66553 , H01L29/6656
摘要： A method is provided for fabricating a gate structure for a semiconductor device in which the gate structure has an inner spacer. A replacement-gate process is used in which material is removed in a gate region to expose a portion of the substrate; a gate dielectric is formed on the exposed portion of the substrate; and an inner spacer layer is formed overlying the gate dielectric and the dielectric material. A silicon layer is then formed which overlies the inner spacer layer. The structure is then planarized so that portions of the silicon layer and inner spacer layer remain in the gate region. A silicide gate structure is then formed from the silicon; the silicide gate structure is separated from dielectric material surrounding the gate by the inner spacer layer. The semiconductor device may include a first gate region and a second gate region with an interface therebetween, with the inner spacer layer covering the interface. When the device has two gate regions, the process may be used in both gate regions, so as to produce separate silicide structures, with an inner spacer separating the two structures.
摘要翻译：提供了一种用于制造半导体器件的栅极结构的方法，其中栅极结构具有内部间隔物。使用替代栅极工艺，其中在栅极区域中去除材料以暴露基板的一部分; 栅极电介质形成在衬底的暴露部分上; 并且形成覆盖栅极电介质和电介质材料的内部间隔层。然后形成覆盖在内间隔层上的硅层。然后将该结构平坦化，使得硅层和内部间隔层的部分保留在栅极区域中。然后从硅形成硅化物栅极结构; 硅化物栅极结构通过内部间隔层与围绕栅极的介电材料分离。半导体器件可以包括第一栅极区域和其间具有界面的第二栅极区域，内部间隔层覆盖界面。当器件具有两个栅极区域时，该工艺可以在两个栅极区域中使用，以便产生分离的硅化物结构，其中分隔两个结构的内部间隔物。

2. 发明授权

US07056794B2 FET gate structure with metal gate electrode and silicide contact 有权
标题翻译： FET栅极结构与金属栅电极和硅化物接触
公开(公告)号：US07056794B2
公开(公告)日：2006-06-06
申请号：US10707757
申请日：2004-01-09
申请人： Victor Ku , An Steegen , Hsing-Jen C. Wann
发明人： Victor Ku , An Steegen , Hsing-Jen C. Wann
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66583 , H01L21/28079 , H01L21/28247 , H01L21/823835 , H01L29/66545
摘要： A method is provided for fabricating a single-metal or dual metal replacement gate structure for a semiconductor device; the structure includes a silicide contact to the gate region. A dummy gate structure and sacrificial gate dielectric are removed to expose a portion of the substrate; a gate dielectric is formed thereon. A metal layer is formed overlying the gate dielectric and the dielectric material. This metal layer may conveniently be a blanket metal layer covering a device wafer. A silicon layer is then formed overlying the metal layer; this layer may also be a blanket wafer. A planarization or etchback process is then performed, so that the top surface of the dielectric material is exposed while other portions of the metal layer and the silicon layer remain in the gate region and have surfaces coplanar with the top surface of the dielectric material. A silicide contact is then formed which is in contact with the metal layer in the gate region.
摘要翻译：提供一种用于制造用于半导体器件的单金属或双金属替代栅极结构的方法; 该结构包括与栅极区域的硅化物接触。去除伪栅极结构和牺牲栅极电介质以暴露衬底的一部分; 在其上形成栅极电介质。形成覆盖栅极电介质和电介质材料的金属层。该金属层可以方便地覆盖覆盖器件晶片的覆盖金属层。然后形成覆盖在金属层上的硅层; 该层也可以是覆盖晶片。然后执行平面化或回蚀工艺，使得介电材料的顶表面被暴露，而金属层和硅层的其它部分保留在栅极区域中并具有与电介质材料的顶表面共面的表面。然后形成与栅极区域中的金属层接触的硅化物接触。

3. 发明授权

US6022771A Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions 失效
标题翻译：具有浅结和侧壁间隔物的半导体器件的制造产生锥形隔离，其中源极和漏极区域与栅极区域相遇
公开(公告)号：US6022771A
公开(公告)日：2000-02-08
申请号：US236691
申请日：1999-01-25
申请人： William Hsioh-Lien Ma , Hsing-Jen C. Wann
发明人： William Hsioh-Lien Ma , Hsing-Jen C. Wann
IPC分类号： H01L29/78 , H01L21/225 , H01L21/336 , H01L27/08 , H01L29/423 , H01L29/786 , H01L21/8238 , H01L23/48 , H01L27/01 , H01L29/76
CPC分类号： H01L29/66628 , H01L21/2257 , H01L29/78 , H01L2924/0002 , Y10S438/978
摘要： A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; and siliciding the top surfaces of the source and drain regions.
摘要翻译：通过提供具有源极和漏极区域和多晶硅栅极区域的半导体衬底来提供具有浅结的半导体器件; 在源极和漏极区上沉积选择性硅; 在形成浅结的源极和漏极区域中提供掺杂剂; 在所述栅极区域的侧壁上形成第一绝缘间隔物; 在所述第一绝缘间隔物上形成第二绝缘侧壁间隔物; 并硅化源极和漏极区域的顶表面。

4. 发明授权

US05998273A Fabrication of semiconductor device having shallow junctions 失效
标题翻译：具有浅结的半导体器件的制造
公开(公告)号：US05998273A
公开(公告)日：1999-12-07
申请号：US236690
申请日：1999-01-25
申请人： William Hsioh-Lien Ma , Hsing-Jen C. Wann
发明人： William Hsioh-Lien Ma , Hsing-Jen C. Wann
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L29/08 , H01L29/423 , H01L21/331
CPC分类号： H01L29/66628 , H01L21/2257 , H01L21/28052 , H01L21/28114 , H01L29/0847 , H01L29/42376 , H01L29/665
摘要： A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions and on the polysilicon gate regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; implanting dopants into the source and drain regions for providing deep junctions and into the polysilicon gate regions; and siliciding the top surfaces of the source and drain regions and polysilicon gate regions.
摘要翻译：通过提供具有源极和漏极区域和多晶硅栅极区域的半导体衬底来提供具有浅结的半导体器件; 在源极和漏极区域和多晶硅栅极区域上沉积选择性硅; 在形成浅结的源极和漏极区域中提供掺杂剂; 在所述栅极区域的侧壁上形成第一绝缘间隔物; 在所述第一绝缘间隔物上形成第二绝缘侧壁间隔物; 将掺杂剂注入到源极和漏极区域中，以提供深的结并进入多晶硅栅极区域; 并且将源极和漏极区域和多晶硅栅极区域的顶表面硅化。

5. 发明授权

US06975133B1 Logic circuits having linear and cellular gate transistors 失效
标题翻译：具有线性和蜂窝状栅极晶体管的逻辑电路
公开(公告)号：US06975133B1
公开(公告)日：2005-12-13
申请号：US10709784
申请日：2004-05-27
申请人： Victor Wing Chung Chan , Hsing-Jen C. Wann , Shih-Fen Huang , Oleg Gluschenkov
发明人： Victor Wing Chung Chan , Hsing-Jen C. Wann , Shih-Fen Huang , Oleg Gluschenkov
IPC分类号： H01L27/02 , H03K17/16 , H03K19/017 , H03K19/094 , H03K19/0948
CPC分类号： H03K19/0948 , H01L27/0203 , H03K19/01707
摘要： A logic circuit is provided with a first inverter having a plurality of linear gate transistors driving a first capacitive load and a second inverter having a plurality of cellular gate transistors driving a second capacitive load. The first inverter is serially connected to the second inverter. The second capacitive load is larger than the first capacitive load.
摘要翻译：逻辑电路设置有具有驱动第一电容性负载的多个线性栅极晶体管的第一反相器和驱动第二电容负载的多个蜂窝状栅极晶体管的第二反相器。第一个逆变器串联连接到第二个逆变器。第二容性负载大于第一容性负载。

6. 发明授权

US5998248A Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region 失效
标题翻译：在隔离区域中制造具有锥形间隔物的浅结的半导体器件
公开(公告)号：US5998248A
公开(公告)日：1999-12-07
申请号：US236693
申请日：1999-01-25
申请人： William Hsioh-Lien Ma , Hsing-Jen C. Wann
发明人： William Hsioh-Lien Ma , Hsing-Jen C. Wann
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L29/08 , H01L29/423 , H01L21/8238
CPC分类号： H01L29/66628 , H01L21/2257 , H01L21/28052 , H01L21/28114 , H01L29/0847 , H01L29/42376 , H01L29/665 , H01L29/66545 , Y10S438/978
摘要： A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; and siliciding the top surfaces of the source and drain regions and polysilicon gate regions.
摘要翻译：通过提供具有源极和漏极区域和多晶硅栅极区域的半导体衬底来提供具有浅结的半导体器件; 在源极和漏极区上沉积选择性硅; 在形成浅结的源极和漏极区域中提供掺杂剂; 在所述栅极区域的侧壁上形成第一绝缘间隔物; 在所述第一绝缘间隔物上形成第二绝缘侧壁间隔物; 并且将源极和漏极区域和多晶硅栅极区域的顶表面硅化。

7. 发明授权

US06268640B1 Forming steep lateral doping distribution at source/drain junctions 失效
标题翻译：在源极/漏极结处形成陡峭的横向掺杂分布
公开(公告)号：US06268640B1
公开(公告)日：2001-07-31
申请号：US09373161
申请日：1999-08-12
申请人： Heemyong Park , Yuan Taur , Hsing-Jen C. Wann
发明人： Heemyong Park , Yuan Taur , Hsing-Jen C. Wann
IPC分类号： H01L2972
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/7836
摘要： A semiconductor device is fabricated by implanting into a semiconductor substrate non-doping ions at a tilt angle of at least about 10° to laterally extend preamorphization of the substrate portion and then implanting into the substrate dopants for providing source/drain extensions or halo doping or both.
摘要翻译：半导体器件通过将半导体衬底注入至少约10°的倾斜角度的非掺杂离子来制造，以横向延伸衬底部分的预变形，然后将其注入到用于提供源极/漏极扩展或晕圈掺杂的衬底掺杂物中，都。

8. 发明授权

US6025242A Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation 失效
标题翻译：通过热氧化制造具有包括绝缘间隔物的浅结的半导体器件，形成锥形隔离
公开(公告)号：US6025242A
公开(公告)日：2000-02-15
申请号：US236689
申请日：1999-01-25
申请人： William Hsioh-Lien Ma , Hsing-Jen C. Wann
发明人： William Hsioh-Lien Ma , Hsing-Jen C. Wann
IPC分类号： H01L21/336 , H01L29/423 , H01L21/8238 , H01L23/48 , H01L27/01 , H01L29/76
CPC分类号： H01L29/66628 , H01L29/78 , H01L2924/0002 , Y10S438/978
摘要： A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; and siliciding the top surfaces of the source and drain regions.
摘要翻译：通过提供具有源极和漏极区域和多晶硅栅极区域的半导体衬底来提供具有浅结的半导体器件; 在源极和漏极区上沉积选择性硅; 在形成浅结的源极和漏极区域中提供掺杂剂; 在所述栅极区域的侧壁上形成第一绝缘间隔物; 在所述第一绝缘间隔物上形成第二绝缘侧壁间隔物; 并硅化源极和漏极区域的顶表面。

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