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1. 发明申请

US20140017894A1 Methods of Manufacturing Semiconductor Devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20140017894A1
公开(公告)日：2014-01-16
申请号：US13546800
申请日：2012-07-11
申请人： Cheng-Hsiung Tsai , Chung-Ju Lee , Hsin-Chieh Yao , Tien-I Bao
发明人： Cheng-Hsiung Tsai , Chung-Ju Lee , Hsin-Chieh Yao , Tien-I Bao
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/02115 , H01L21/31144 , H01L21/76816
摘要： Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a material layer is formed over a workpiece. The workpiece includes a first portion, a second portion, and a hard mask disposed between the first portion and the second portion. The material layer is patterned, and first spacers are formed on sidewalls of the patterned material layer. The patterned material layer is removed, and the second portion of the workpiece is patterned using the first spacers as an etch mask. The first spacers are removed, and second spacers are formed on sidewalls of the patterned second portion of the workpiece. The patterned second portion of the workpiece is removed, and the hard mask of the workpiece is patterned using the second spacers as an etch mask. The first portion of the workpiece is patterned using the hard mask as an etch mask.
摘要翻译：公开了制造半导体器件的方法。在一个实施例中，材料层形成在工件上。工件包括设置在第一部分和第二部分之间的第一部分，第二部分和硬掩模。图案化材料层，并且在图案化材料层的侧壁上形成第一间隔物。去除图案化的材料层，并且使用第一间隔件作为蚀刻掩模来对工件的第二部分进行图案化。去除第一间隔物，并且在工件的图案化第二部分的侧壁上形成第二间隔物。去除工件的图案化的第二部分，并且使用第二间隔件作为蚀刻掩模来对工件的硬掩模进行图案化。使用硬掩模作为蚀刻掩模来对工件的第一部分进行图案化。

2. 发明授权

US08513821B2 Overlay mark assistant feature 有权
公开(公告)号：US08513821B2
公开(公告)日：2013-08-20
申请号：US12784581
申请日：2010-05-21
申请人： Hsin-Chieh Yao , Hsien-Cheng Wang , Chien-Kai Huang , Chun-Kuang Chen
发明人： Hsin-Chieh Yao , Hsien-Cheng Wang , Chien-Kai Huang , Chun-Kuang Chen
IPC分类号： H01L23/544 , H01L21/28
CPC分类号： H01L21/28 , G03F7/70633 , G03F7/70683 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.

3. 发明申请

US20110285036A1 OVERLAY MARK ASSISTANT FEATURE 有权
标题翻译：超标记助理功能
公开(公告)号：US20110285036A1
公开(公告)日：2011-11-24
申请号：US12784581
申请日：2010-05-21
申请人： Hsin-Chieh Yao , Hsien-Cheng Wang , Chien-Kai Huang , Chun-Kuang Chen
发明人： Hsin-Chieh Yao , Hsien-Cheng Wang , Chien-Kai Huang , Chun-Kuang Chen
IPC分类号： H01L23/544 , H01L21/28
CPC分类号： H01L21/28 , G03F7/70633 , G03F7/70683 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.
摘要翻译：公开了一种用于对准的方法和装置。示例性装置包括具有对准区域的基板; 在基板的对准区域中的对准特征; 以及设置在对准特征内的虚拟特征。虚拟特征的尺寸小于对准标记检测器的分辨率。

4. 发明申请

US20140065816A1 DIELECTRIC FORMATION 审中-公开
标题翻译：电介质形成
公开(公告)号：US20140065816A1
公开(公告)日：2014-03-06
申请号：US13600504
申请日：2012-08-31
申请人： Tsung-Jung Tsai , Hsin-Chieh Yao , Chien-Hua Huang , Chung-Ju Lee
发明人： Tsung-Jung Tsai , Hsin-Chieh Yao , Chien-Hua Huang , Chung-Ju Lee
IPC分类号： H01L21/768
CPC分类号： H01L21/76885 , H01L21/76831
摘要： Among other things, one or more techniques for forming a low k dielectric around a metal line during an integrated circuit (IC) fabrication process are provided. In an embodiment, a metal line is formed prior to forming a surrounding low k dielectric layer around the metal line. In an embodiment, the metal line is formed by filling a trench space in a skeleton layer with metal. In this embodiment, the skeleton layer is removed to form a dielectric space in a different location than the trench space. The dielectric space is then filled with a low k dielectric material to form a surrounding low k dielectric layer around the metal line. In this manner, damage to the surrounding low k dielectric layer, that would otherwise occur if the surrounding low k dielectric layer was etched, for example, is mitigated.
摘要翻译：其中，提供了在集成电路（IC）制造过程中用于在金属线周围形成低k电介质的一种或多种技术。在一个实施例中，在围绕金属线形成周围的低k电介质层之前形成金属线。在一个实施例中，通过用金属填充骨架层中的沟槽空间来形成金属线。在该实施例中，除去骨架层以在与沟槽空间不同的位置形成电介质空间。然后用低k电介质材料填充电介质空间，以在金属线周围形成周围的低k电介质层。以这种方式，例如，如果周围的低k电介质层被蚀刻，则会损坏周围的低k电介质层，否则会被破坏。

5. 发明授权

US09349595B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09349595B2
公开(公告)日：2016-05-24
申请号：US13546800
申请日：2012-07-11
申请人： Cheng-Hsiung Tsai , Chung-Ju Lee , Hsin-Chieh Yao , Tien-I Bao
发明人： Cheng-Hsiung Tsai , Chung-Ju Lee , Hsin-Chieh Yao , Tien-I Bao
IPC分类号： H01L21/311 , H01L21/033 , H01L21/768 , H01L21/02
CPC分类号： H01L21/0337 , H01L21/02115 , H01L21/31144 , H01L21/76816
摘要： Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a material layer is formed over a workpiece. The workpiece includes a first portion, a second portion, and a hard mask disposed between the first portion and the second portion. The material layer is patterned, and first spacers are formed on sidewalls of the patterned material layer. The patterned material layer is removed, and the second portion of the workpiece is patterned using the first spacers as an etch mask. The first spacers are removed, and second spacers are formed on sidewalls of the patterned second portion of the workpiece. The patterned second portion of the workpiece is removed, and the hard mask of the workpiece is patterned using the second spacers as an etch mask. The first portion of the workpiece is patterned using the hard mask as an etch mask.
摘要翻译：公开了制造半导体器件的方法。在一个实施例中，材料层形成在工件上。工件包括设置在第一部分和第二部分之间的第一部分，第二部分和硬掩模。图案化材料层，并且在图案化材料层的侧壁上形成第一间隔物。去除图案化的材料层，并且使用第一间隔件作为蚀刻掩模来对工件的第二部分进行图案化。去除第一间隔物，并且在工件的图案化第二部分的侧壁上形成第二间隔物。去除工件的图案化的第二部分，并且使用第二间隔件作为蚀刻掩模来对工件的硬掩模进行图案化。使用硬掩模作为蚀刻掩模来对工件的第一部分进行图案化。

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