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1. 发明授权

US06383863B1 Approach to integrate salicide gate for embedded DRAM devices 有权
标题翻译：为嵌入式DRAM设备集成自杀门的方法
公开(公告)号：US06383863B1
公开(公告)日：2002-05-07
申请号：US09963595
申请日：2001-09-27
申请人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Chung-Wei Chang , Kuo-Chyuan Tzeng
发明人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Chung-Wei Chang , Kuo-Chyuan Tzeng
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/76889 , H01L21/76897 , H01L27/10873 , H01L27/10888 , H01L28/84 , H01L28/90 , H01L29/66545
摘要： A process for integrating the formation of a salicide layer on DRAM word line structures, and on a bit line contact structure, has been developed. The process features selective etch back of the insulator layers embedding the tapered shaped bit line contact, and the tapered shape capacitor structures, exposing top surface portions of polysilicon word line structures. The selective etch back procedure also results in formation of insulator spacers on the sides of the tapered bit line contact, and capacitor structures, allowing a subsequent salicide procedure to form metal suicide layers only on the exposed top surfaces of the DRAM word line, bit line contact, and capacitor structures.
摘要翻译：已经开发了一种用于将自对准硅化物层形成在DRAM字线结构上以及位线接触结构上的过程。该工艺具有嵌入锥形位线接触件的绝缘体层的选择性回蚀和锥形形状电容器结构，暴露多晶硅字线结构的顶表面部分。选择性回蚀程序还导致在锥形位线接触和电容器结构的侧面上形成绝缘体间隔物，并且允许随后的自对准硅化物程序仅在DRAM字线，位线的暴露的顶表面上形成金属硅化物层接触和电容器结构。

2. 发明授权

US06808980B2 Method of process simplification and eliminating topography concerns for the creation of advanced 1T-RAM devices 有权
标题翻译：过程简化的方法和消除创建高级1T-RAM器件的地形问题
公开(公告)号：US06808980B2
公开(公告)日：2004-10-26
申请号：US10310486
申请日：2002-12-05
申请人： Chung-Yi Chen , Min-Hsiung Chiang , Hsien-Yuan Chang
发明人： Chung-Yi Chen , Min-Hsiung Chiang , Hsien-Yuan Chang
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L27/10867
摘要： A new method and structure is provided for the creation of a 1T-RAM cell. Shallow Trench Isolation (STI) regions are provided over a substrate. A 3D capacitor area is defined over the substrate, a patterned layer of polysilicon or HSG polysilicon is created aligned with the 3D capacitor area, providing the bottom plate of a 3D capacitor. Gate oxide is grown to form a dielectric for CMOS gate electrodes and the 3D capacitor dielectric. A patterned layer of polysilicon is created, defining gate electrodes and 3D capacitor upper plates.
摘要翻译：提供了一种新的方法和结构来创建1T-RAM单元。在衬底上提供浅沟槽隔离（STI）区域。三维电容器区域被限定在衬底上，多晶硅或HSG多晶硅的图案化层被创建成与3D电容器区域对准，从而提供3D电容器的底板。生长栅极氧化物以形成用于CMOS栅电极和3D电容器电介质的电介质。产生多晶硅图案层，限定栅电极和3D电容器上板。

3. 发明授权

US06656786B2 MIM process for logic-based embedded RAM having front end manufacturing operation 有权
标题翻译：用于具有前端制造操作的基于逻辑的嵌入式RAM的MIM工艺
公开(公告)号：US06656786B2
公开(公告)日：2003-12-02
申请号：US10000896
申请日：2001-11-02
申请人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Tazy-Schiuan Yang
发明人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Tazy-Schiuan Yang
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10814 , H01L27/10894 , H01L28/60 , Y10S977/888
摘要： A method and system for manufacturing an MIM capacitor for utilization with a logic-based embedded DRAM device. At least one transistor, an interlayer dielectric, at least one contact and at least one metal one layer are generally formed on a substrate during a front end manufacturing operation of the capacitor on the substrate. An inter-metal dielectric layer is deposited upon the substrate, followed thereafter by a chemical mechanical polishing operation. Additionally, a lithographic operation is performed upon the substrate. Also, at least one dielectric deposition layer is generally on the substrate, followed thereafter by a chemical mechanical polishing operation and a stop on an oxide layer formed on the substrate. At least one metal two layer may then be formed on substrate and associated layers thereof, thereby resulting in the formation of a capacitor fully compatible with logic-based devices and processes thereof.
摘要翻译：一种制造用于利用基于逻辑的嵌入式DRAM器件的MIM电容器的方法和系统。在基板上的电容器的前端制造操作期间，通常在基板上形成至少一个晶体管，层间电介质，至少一个触点和至少一个金属层。金属介电层沉积在基板上，其后通过化学机械抛光操作。另外，在基板上执行光刻操作。此外，至少一个电介质沉积层通常在衬底上，随后通过化学机械抛光操作和在形成在衬底上的氧化物层上的停止。然后可以在衬底及其相关层上形成至少一个金属二层，从而形成与基于逻辑的器件及其工艺完全兼容的电容器。

4. 发明授权

US6146987A Method for forming a contact plug over an underlying metal line using an etching stop layer 有权
标题翻译：使用蚀刻停止层在下面的金属线上形成接触塞的方法
公开(公告)号：US6146987A
公开(公告)日：2000-11-14
申请号：US383123
申请日：1999-08-25
申请人： Chien-chun Wang , Eddie Chiu , Chung-Yi Chen , Hsien-Yuan Chang
发明人： Chien-chun Wang , Eddie Chiu , Chung-Yi Chen , Hsien-Yuan Chang
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76834
摘要： A method for forming a contact plug that lands on a metal line of an interconnect structure formed on a semiconductor substrate. First, a first insulating layer is formed atop the substrate and between gaps in the interconnect structure. Next, an etching stop layer is formed on the first insulating layer. A second insulating layer is formed atop the etching stop layer. The second insulating layer is patterned and etched, stopping at the etching stop layer, to form a contact opening. The portion of the etching stop layer left exposed by the contact opening is removed. Finally, a barrier metal layer is formed along the walls of the contact opening and a conducting layer is deposited into the contact opening.
摘要翻译：一种形成在半导体衬底上形成的互连结构的金属线上的接触插塞的方法。首先，在基板顶部和互连结构的间隙之间形成第一绝缘层。接下来，在第一绝缘层上形成蚀刻停止层。第二绝缘层形成在蚀刻停止层的顶部。对第二绝缘层进行图案化和蚀刻，在蚀刻停止层处停止形成接触开口。除去由接触开口露出的蚀刻停止层的部分。最后，沿着接触开口的壁形成阻挡金属层，并且导电层沉积到接触开口中。

5. 发明授权

US06656785B2 MIM process for logic-based embedded RAM 有权
标题翻译：基于逻辑的嵌入式RAM的MIM过程
公开(公告)号：US06656785B2
公开(公告)日：2003-12-02
申请号：US09978421
申请日：2001-10-15
申请人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang
发明人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/31604 , H01L27/10855 , H01L27/10894 , H01L28/55 , H01L28/91
摘要： A method for forming a metal-interlayer-metal (MIM) device in an embedded memory device, including semiconductor devices thereof. An MIM device can be formed upon a semiconductor substrate utilizing no more than one additional photo mask layer prior to the implementation of a back-end-of-line (BEOL) semiconductor fabrication operation, such that the MIM device can be configured as a low temperature MIM device that is fully compatible with logical semiconductor devices, thereby reducing associated manufacturing costs. The MIM device may be configured as an MIM capacitor for logic-based embedded DRAM devices, resulting in a high capacitance performed via an effective area extension of DRAM cell capacitors. Additonally, a low-temperature MIM capacitor thereof may be readily integrated for both Cu (Copper) and AlCu (Aluminum Copper) BEOL fabrication processes.
摘要翻译：一种在包括其半导体器件的嵌入式存储器件中形成金属 - 层间金属（MIM）器件的方法。 MIM器件可以在实施后端（BEOL）半导体制造操作之前利用不超过一个附加光掩模层在半导体衬底上形成，使得MIM器件可以被配置为低与逻辑半导体器件完全兼容，从而降低相关的制造成本。 MIM器件可以被配置为用于基于逻辑的嵌入式DRAM器件的MIM电容器，导致通过DRAM单元电容器的有效区域扩展来执行高电容。此外，其中的低温MIM电容器可以容易地集成在Cu（铜）和AlCu（Aluminum Copper）BEOL制造工艺中。

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