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1. 发明授权

US07073117B1 Method and apparatus for generating bit errors in a forward error correction (FEC) system to estimate power dissipation characteristics of the system 有权
标题翻译：用于在前向纠错（FEC）系统中产生位错误以估计系统的功率耗散特性的方法和装置
公开(公告)号：US07073117B1
公开(公告)日：2006-07-04
申请号：US10366250
申请日：2003-02-13
申请人： Howard H. Ireland , Jeffery T. Nichols
发明人： Howard H. Ireland , Jeffery T. Nichols
IPC分类号： H03M13/03
CPC分类号： H03M13/01
摘要： A method and apparatus for generating and inserting bit errors in data words that have been encoded in a forward error correction (FEC) system in order to estimate power dissipation. In accordance with the present invention, it has been determined that a burst error generator that is capable of erroring the maximum number of correctable data bits in every FEC encoded frame, which allows the designer to accurately produce test vectors that are suitable for use in commercially available power estimation tools. In addition, after the IC is produced, the burst error generator of the present invention can be enabled to provide real-time FEC power dissipation data for use in system thermal modeling, thus obviating the need to use costly external devices that emulate a given error rate. Furthermore, the power dissipation data obtained in real-time may be used to refine the initial design power estimate, which will then allow the designer to develop a more accurate prediction of power consumption for future IC designs. Thus, the burst error generator of the present invention is capable of reducing iterations of IC designs by accurately estimating the worst-case power dissipation of FEC decoders.
摘要翻译：一种用于产生和插入在前向纠错（FEC）系统中编码的数据字中的位错误以估计功耗的方法和装置。根据本发明，已经确定了能够错误在每个FEC编码帧中可校正数据位的最大数量的突发错误发生器，这允许设计者准确地产生适合于商业使用的测试向量可用的功率估计工具。此外，在IC产生之后，本发明的脉冲串错误发生器能够提供用于系统热建模的实时FEC功率耗散数据，从而避免使用模拟给定误差的昂贵的外部设备率。此外，实时获得的功耗数据可用于优化初始设计功率估计，从而允许设计者开发更准确的将来IC设计的功耗预测。因此，本发明的突发错误发生器能够通过精确地估计FEC解码器的最坏情况的功耗来减少IC设计的迭代。

2. 发明授权

US07096408B1 Method and apparatus for computing the error locator polynomial in a decoder of a forward error correction (FEC) system 有权
标题翻译：用于在前向纠错（FEC）系统的解码器中计算误差定位多项式的方法和装置
公开(公告)号：US07096408B1
公开(公告)日：2006-08-22
申请号：US10371121
申请日：2003-02-21
申请人： Howard H. Ireland , Jeffery T. Nichols
发明人： Howard H. Ireland , Jeffery T. Nichols
IPC分类号： H03M13/15 , H03M13/09
CPC分类号： G06F7/724 , H03M13/1515 , H03M13/152 , H03M13/153 , H03M13/158 , H03M13/159 , H03M13/616
摘要： A method and apparatus for performing quickly and efficiently generating the error correction polynomial. In accordance with the present invention, multiple coefficients of the syndrome vector are processed in parallel by a Berlekamp algorithm logic block of the present invention. The Berlekamp algorithm's iterations can be performed in less than 60 clock cycles for a large order error correction polynomial, thereby enabling the polynomial to be generated very rapidly. In order to perform the Berlekamp algorithm at such a high rate of speed, Galois field multiplier logic is utilized in performing the algorithm. Furthermore, because of the large number of logical multiplication and addition operations that are performed in parallel, the Galois filed multiplier logic in accordance with the preferred embodiment of the present invention is configured in such a way that redundancy in processing polynomial coefficients is greatly reduced, which enables the number of logic gates needed to implement the Galois field multiplier logic to be vastly reduced. This reduction in the number of gates used for this purpose reduces area and power consumption requirements.
摘要翻译：一种用于快速有效地生成纠错多项式的方法和装置。根据本发明，通过本发明的Berlekamp算法逻辑块并行处理多个系数的校正子向量。 Berlekamp算法的迭代可以在小于60个时钟周期内执行大量的纠错多项式，从而使得能够非常快速地生成多项式。为了以如此高的速率执行Berlekamp算法，伽罗瓦域乘法器逻辑被用于执行算法。此外，由于并行执行的大量逻辑乘法和加法运算，根据本发明的优选实施例的伽罗瓦域乘法器逻辑被配置成使处理多项式系数中的冗余大大减少，这使得实现伽罗瓦域乘法器逻辑所需的逻辑门的数量大大减少。用于此目的的门数量的减少减少了面积和功耗要求。

3. 发明授权

US07058876B1 Method and apparatus for use in a decoder of a forward error correction (FEC) system for locating bit errors in a error locator polynomial 有权
标题翻译：在用于定位误差定位多项式中的位错误的前向纠错（FEC）系统的解码器中使用的方法和装置
公开(公告)号：US07058876B1
公开(公告)日：2006-06-06
申请号：US10371708
申请日：2003-02-22
申请人： Howard H. Ireland , Jeffery T. Nichols
发明人： Howard H. Ireland , Jeffery T. Nichols
IPC分类号： H03M13/15
CPC分类号： H03M13/616 , G06F7/724 , H03M13/152 , H03M13/153 , H03M13/1545 , H03M13/158 , H03M13/159
摘要： The present invention provides a method and apparatus for quickly and efficiently processing an error correction polynomial to locate bit errors using a Chien search algorithm. In accordance with the present invention, it has been determined that multiplying the Λ coefficients of the error locator polynomial by a scaling vector prior to performing the Chien search algorithm matrix operations, it possible to use constant coefficients in the matrix multiply logic. This enables a relatively small amount of logic to be used to perform the matrix multiplication operations of the Chien search algorithm. The Chien search algorithm logic of the present invention is configured to perform many matrix multiply operations in parallel, which enables the Chien search algorithm to be executed very quickly to locate the bit errors in the error locator polynomial. Such a large number of matrix multiply operations would normally require a very large number of gates. However, the constant coefficient matrix multiply logic configuration of the present invention that is made possible by the aforementioned scaling significantly limits the amount of logic needed to perform the matrix multiply operations. Therefore, the present invention enables very high-speed throughput with respect to error correction, and does so using a relatively small amount of logic. This renders the decoder of the present invention suitable for use in high data rate systems. Furthermore, the use of a relatively small amount of logic limits area and power consumption requirements.
摘要翻译：本发明提供一种用于使用Chien搜索算法快速有效地处理纠错多项式以定位位错误的方法和装置。根据本发明，已经确定在执行Chien搜索算法矩阵运算之前将误差定位多项式的λ系数乘以缩放向量，可以在矩阵乘法逻辑中使用常数系数。这使得可以使用相对较少量的逻辑来执行Chien搜索算法的矩阵乘法运算。本发明的Chien搜索算法逻辑被配置为并行执行许多矩阵乘法运算，这使得能够非常快速地执行Chien搜索算法来定位误差定位器多项式中的位错误。这样大量的矩阵乘法运算通常需要非常大量的门。然而，通过上述缩放使本发明实现的常数系数矩阵乘法逻辑配置显着地限制了执行矩阵乘法运算所需的逻辑量。因此，本发明能够在纠错方面实现非常高速的吞吐量，并且使用相对少量的逻辑。这使得本发明的解码器适用于高数据速率系统。此外，使用相对较少量的逻辑限制面积和功耗要求。

4. 发明授权

US07003708B1 Method and apparatus for generating bit errors with a poisson error distribution 有权
标题翻译：用泊松误差分布产生位错误的方法和装置
公开(公告)号：US07003708B1
公开(公告)日：2006-02-21
申请号：US10365877
申请日：2003-02-13
申请人： Howard H. Ireland , Jeffery T. Nichols
发明人： Howard H. Ireland , Jeffery T. Nichols
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G11B20/1816 , H03M13/01
摘要： A method and apparatus that enable a Poisson distribution to be approximated by generating random bit sequences over a number of clock cycles. The apparatus of the present invention comprises a Poisson distribution module that includes logic configured to modulo-2 add at least two pseudo-random bit sequences (PRBSs) together to generate a number of PRBSs, which are then compared to a threshold bit sequence. The result of the comparison is a random bit sequence. Over a number of clock cycles, the random bit sequences produced approximate a Poisson distribution. The present invention can be used to evaluate the performance of communications systems by modulo-2 adding these random bit sequences with encoded data words to insert errors into the encoded data words, and then determining how well the communications system decodes and corrects the errors in the encoded data words. The present invention is particularly useful in this environment because the true distribution of errors in encoded data words transmitted over communications links generally is Poisson in nature.
摘要翻译：通过在多个时钟周期内产生随机比特序列来使泊松分布近似的方法和装置。本发明的装置包括泊松分配模块，其包括配置成模2加入至少两个伪随机比特序列（PRBS）在一起以产生多个PRBS的逻辑，然后将其与阈值比特序列进行比较。比较结果是随机比特序列。在多个时钟周期中，产生的随机比特序列近似泊松分布。本发明可用于通过模2加上具有编码数据字的这些随机比特序列以将错误插入到编码数据字中，然后确定通信系统如何解码和校正错误的方式来评估通信系统的性能编码数据字。本发明在这种环境中特别有用，因为通过通信链路传输的编码数据字中的错误的真实分布通常是泊松性质。

5. 发明授权

US06986097B1 Method and apparatus for generating parity bits in a forward error correction (FEC) system 有权
标题翻译：用于在前向纠错（FEC）系统中产生奇偶校验位的方法和装置
公开(公告)号：US06986097B1
公开(公告)日：2006-01-10
申请号：US10371560
申请日：2003-02-21
申请人： Howard H. Ireland , Jeffery T. Nichols
发明人： Howard H. Ireland , Jeffery T. Nichols
IPC分类号： G06F11/10
CPC分类号： H03M13/47 , H03M13/152 , H03M13/615
摘要： A method and apparatus for performing parity bit generation. The apparatus of the present invention comprises a parity bit generator that multiplies words comprising message bits by a partial parity multiplication sub-matrix to generate intermediate parity values, and recursively adds (modulo-2) respective intermediate values together so that by the end of the recursive process, a final parity vector exists. This final parity vector can then be added to a message word to create a code word. By recursively using the partial parity multiplication sub-matrix in this way, the number of gates needed to perform parity bit generation is kept relatively small. Consequently the amount of power consumed by the parity bit generator during parity bit generation is relatively small. This is in contrast to typical parity bit generators, which multiply all of the message bits by a full parity multiplication matrix without recursion. The typical non-recursive process, which utilizes the complete parity multiplication matrix, requires a very large number of gates and a large area on an IC to implement the parity bit generator. Also, because of the large number of gates associated with parity bit generators that use the typical approach, those generators consume a large amount of power. The method and apparatus of the present invention are suitable for use with an encoder of a forward error correction (FEC) system.
摘要翻译：一种用于执行奇偶校验位产生的方法和装置。本发明的装置包括奇偶校验位产生器，其将包含消息比特的单词乘以部分奇偶校验乘法子矩阵以产生中间奇偶校验值，并将各个中间值递归（模2）加在一起，使得在递归过程，存在最终奇偶校验向量。然后可以将该最终奇偶校验向量添加到消息字以创建代码字。通过以这种方式递归地使用部分奇偶校验乘法子矩阵，执行奇偶校验位产生所需的门数保持相对较小。因此，奇偶位产生器在奇偶校验位产生期间消耗的功率量相对较小。这与典型的奇偶校验位产生器相反，奇偶校验位生成器将所有消息位乘以完全奇偶校验乘法矩阵而不进行递归。利用完整的奇偶校验乘法矩阵的典型非递归过程需要非常大量的门和IC上的大面积来实现奇偶位产生器。此外，由于与使用典型方法的奇偶校验位发生器相关联的大量门，这些发生器消耗大量的功率。本发明的方法和装置适用于前向纠错（FEC）系统的编码器。

6. 发明授权

US5266953A Adaptive fixed-threshold pulse time-of-arrival detection apparatus for precision distance measuring equipment applications 失效
标题翻译：用于精密距离测量设备应用的自适应固定阈值脉冲到达时间检测装置
公开(公告)号：US5266953A
公开(公告)日：1993-11-30
申请号：US739074
申请日：1991-08-01
申请人： Robert J. Kelly , Michael G. Biggs , Howard H. Ireland , Gary A. Drutch , Janice A. Winter
发明人： Robert J. Kelly , Michael G. Biggs , Howard H. Ireland , Gary A. Drutch , Janice A. Winter
IPC分类号： G01R29/027 , G01S13/78 , G01S13/08
CPC分类号： G01S13/785 , G01R29/0276
摘要： An apparatus to be employed within a precision distance measuring system for estimating pulse time-of-arrival. The apparatus facilitates the use of an Adaptive Fixed Threshold method for such estimation. The invention compensates for pulse time detection errors induced by variations in incident pulse amplitude and shape by adjusting the estimated time-of-arrival. This adjustment is performed as a function of the measured pulse slope between two low-amplitude threshold levels through the use of a predetermined reference table of error adjustment times.
摘要翻译：用于估计脉冲到达时间的精密距离测量系统中使用的装置。该装置便于对这种估计使用自适应固定阈值方法。本发明通过调整估计的到达时间来补偿由入射脉冲振幅和形状的变化引起的脉冲时间检测误差。通过使用预定的误差调整时间的参考表，该调整是通过两个低振幅阈值水平之间的测量脉冲斜率来执行的。

7. 发明授权

US07113968B1 Method and apparatus for efficiently performing Galois field multiplication 有权
公开(公告)号：US07113968B1
公开(公告)日：2006-09-26
申请号：US10371298
申请日：2003-02-21
申请人： Howard H. Ireland , Jeffrey T. Nichols
发明人： Howard H. Ireland , Jeffrey T. Nichols
IPC分类号： G06F7/00
CPC分类号： G06F7/724
摘要： A method and apparatus for performing Galois field multiplication with reduced redundancy. Generally, multiplication by a Galois field multiplier involves the multiplication of two polynomials modulo another polynomial. The Galois field multiplier has two Galois Field elements in a field of GF(2n) that correspond to the binary polynomials A[X] and B[X]: A[X]=an-1Xn-1+an-2Xn-2+an-3Xn-3+ . . . a1X+a0, B[X]=bn-1Xn-1+bn-2Xn-2+bn-3Xn-3+ . . . b1X+b0, where n corresponds to a number of terms in a Galois extension field of the Galois multiplier, and n-1 is an order of the polynomial A[X]. Premultiplier logic translates the binary polynomial A[X] into a binary vector cr, where r is the number of terms of the vector. The premultiplier logic is configured to modulo-2 add together various coefficients of the a0 through an-1, coefficients to produce various terms c0 through cr-1 of the cr binary vector. Binary multiplication and addition logic then operates on the c0 through cr-1 coefficients and the b0 through bn-1 coefficients to produce d0 through dn coefficients of a binary polynomial D[X]. The coefficients d0 through dn are the output of the Galois field multiplier. Utilization of the premultiplier logic component reduces the amount of binary multiplication and addition logic needed to produce the coefficients d0 through dn of the binary polynomial D[X].

8. 发明授权

US07039854B1 Method and apparatus for performing syndrome computation in a decoder of a forward error correction (FEC) system 有权
标题翻译：用于在前向纠错（FEC）系统的解码器中执行校正子计算的方法和装置
公开(公告)号：US07039854B1
公开(公告)日：2006-05-02
申请号：US10371563
申请日：2003-02-21
申请人： Howard H. Ireland , Jeffery T. Nichols
发明人： Howard H. Ireland , Jeffery T. Nichols
IPC分类号： G06F11/10
CPC分类号： H03M13/1575 , H03M13/159
摘要： A method and apparatus for performing syndrome computation in a decoder of a forward error correction (FEC) system. Syndrome computation logic of the decoder uses a partial parity-check matrix to recursively generate intermediate syndrome vectors based on a code word received by the decoder and to modulo-2 add the recursively generated intermediate syndrome vectors together until a final resolved syndrome vector has been generated. This recursive use of the partial parity-check matrix enables the syndrome computations to be performed very quickly so that the decoder is suitable for use in high data rate systems and provides a very large reduction in the amount of logic needed to perform the syndrome vector computations. The reduction in the syndrome computation logic results in reduced area requirements for the logic as well as reduced power requirements.
摘要翻译：一种用于在前向纠错（FEC）系统的解码器中执行校正子计算的方法和装置。解码器的综合征计算逻辑使用部分奇偶校验矩阵来递归地生成基于由解码器接收的码字的中间校正子向量，并且将2递归生成的中间综合征向量加到一起，直到生成最终解决的综合征矢量。这种部分奇偶校验矩阵的递归使用使得能够非常快速地执行校正子计算，使得解码器适合于在高数据速率系统中使用并且提供执行校正子向量计算所需的逻辑量的非常大的减少。综合计算逻辑的减少导致了对逻辑的减少的面积要求以及降低的功率需求。

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