专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08243479B2 On-die anti-resonance structure for integrated circuit 有权
标题翻译：用于集成电路的片上反共振结构
公开(公告)号：US08243479B2
公开(公告)日：2012-08-14
申请号：US13235906
申请日：2011-09-19
申请人： Houfei Chen
发明人： Houfei Chen
IPC分类号： H02H3/22 , H02M1/14
CPC分类号： G06F1/26 , H01L23/64 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to reduce the output impedance of the power delivery system at the resonance frequency.
摘要翻译：描述了用于降低集成电路组件中芯片封装谐振的影响的结构和方法。采用串联RLC电路来降低功率输送系统在谐振频率下的输出阻抗。

2. 发明申请

US20120007669A1 ON-DIE ANTI-RESONANCE STRUCTURE FOR INTEGRATED CIRCUIT 有权
标题翻译：集成电路的电阻抗谐振结构
公开(公告)号：US20120007669A1
公开(公告)日：2012-01-12
申请号：US13235906
申请日：2011-09-19
申请人： Houfei Chen
发明人： Houfei Chen
IPC分类号： H01L27/00
CPC分类号： G06F1/26 , H01L23/64 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to reduce the output impedance of the power delivery system at the resonance frequency.
摘要翻译：描述了用于降低集成电路组件中芯片封装谐振的影响的结构和方法。采用串联RLC电路来降低功率输送系统在谐振频率下的输出阻抗。

3. 发明申请

US20100284134A1 SUBSTRATES, SYSTEMS, AND DEVICES INCLUDING STRUCTURES FOR SUPPRESSING POWER AND GROUND PLANE NOISE, AND METHODS FOR SUPPRESSING POWER AND GROUND PLANE NOISE 有权
标题翻译：基板，系统和装置，包括用于抑制电力和接地平面噪声的结构，以及用于抑制电力和接地平面噪声的方法
公开(公告)号：US20100284134A1
公开(公告)日：2010-11-11
申请号：US12842637
申请日：2010-07-23
申请人： Houfei Chen , Shiyou Zhao
发明人： Houfei Chen , Shiyou Zhao
IPC分类号： G06F1/16 , H05K1/00 , H05K1/16 , H05K7/00 , H05K1/11
CPC分类号： H05K1/0216 , G11C5/04 , G11C5/063 , H05K1/0298 , H05K1/162 , H05K2201/09309 , H05K2201/09636 , H05K2201/09981 , H05K2203/0733 , Y10T29/4913 , Y10T29/49155
摘要： Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The at least one noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.
摘要翻译：具有电源和接地层的衬底，例如印刷电路板，包括至少一个噪声抑制结构，其被配置为抑制通过电力平面和接地平面中的至少一个传播的电波。所述至少一个噪声抑制结构可以包括从所述功率平面大致朝向所述接地平面延伸的电力平面延伸部，以及从所述接地平面大致向所述电力平面延伸的接地平面延伸部。接地平面延伸部可以与动力平面延伸部分离距离小于分离动力和接地平面的距离。电子器件组件和系统包括这样的衬底。用于抑制电力平面和接地平面中的至少一个中的噪声的方法包括在电源和接地层之间提供这种噪声抑制结构。

4. 发明申请

US20070007031A1 Method for Forming a Circuit Board Via Structure for High Speed Signaling 失效
标题翻译：通过高速信号结构形成电路板的方法
公开(公告)号：US20070007031A1
公开(公告)日：2007-01-11
申请号：US11533005
申请日：2006-09-19
申请人： Shiyou Zhao , Houfei Chen , Hao Wang
发明人： Shiyou Zhao , Houfei Chen , Hao Wang
IPC分类号： H05K1/03
CPC分类号： H05K3/429 , H05K1/0222 , H05K1/115 , H05K1/162 , H05K3/10 , H05K3/42 , H05K2201/09809 , Y10T29/49155 , Y10T29/49156 , Y10T29/4916 , Y10T29/49163 , Y10T29/49165 , Y10T29/49167
摘要： One embodiment of the invention comprises an improved via structure for use in a printed circuit board (PCB), and method for fabricating the same. The via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal plane. To minimize EM disturbance between the power and ground planes, signal loss due to signal return current, and via-to-via coupling, the via is shielded within two concentric cylinders, each coupled to one of the power and ground planes.
摘要翻译：本发明的一个实施例包括用于印刷电路板（PCB）的改进的通孔结构及其制造方法。该通孔允许信号从（PCB）中的一个信号平面传递到另一个信号面，并且这样做会超过信号平面之间的电源和接地平面。为了最小化电源和接地层之间的电磁干扰，由于信号返回电流引起的信号损耗以及通孔到通孔耦合，通孔被屏蔽在两个同心圆柱体中，每个连接到电源和接地层之一。

5. 发明授权

US07778039B2 Substrates, systems, and devices including structures for suppressing power and ground plane noise, and methods for suppressing power and ground plane noise 有权
标题翻译：包括用于抑制电力和接地平面噪声的结构的基板，系统和装置，以及用于抑制电力和接地平面噪声的方法
公开(公告)号：US07778039B2
公开(公告)日：2010-08-17
申请号：US11430540
申请日：2006-05-08
申请人： Houfei Chen , Shiyou Zhao
发明人： Houfei Chen , Shiyou Zhao
IPC分类号： H05K1/18
CPC分类号： H05K1/0216 , G11C5/04 , G11C5/063 , H05K1/0298 , H05K1/162 , H05K2201/09309 , H05K2201/09636 , H05K2201/09981 , H05K2203/0733 , Y10T29/4913 , Y10T29/49155
摘要： Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.
摘要翻译：具有电源和接地层的衬底，例如印刷电路板，包括至少一个噪声抑制结构，其被配置为抑制通过电力平面和接地平面中的至少一个传播的电波。噪声抑制结构可以包括从功率平面大体上朝向接地平面延伸的电源平面延伸，以及从接地平面大致朝向电力平面延伸的接地平面延伸。接地平面延伸部可以与动力平面延伸部分离距离小于分离动力和接地平面的距离。电子器件组件和系统包括这样的衬底。用于抑制电力平面和接地平面中的至少一个中的噪声的方法包括在电源和接地层之间提供这种噪声抑制结构。

6. 发明授权

US07459638B2 Absorbing boundary for a multi-layer circuit board structure 有权
标题翻译：多层电路板结构的吸收边界
公开(公告)号：US07459638B2
公开(公告)日：2008-12-02
申请号：US11114589
申请日：2005-04-26
申请人： Houfei Chen , Shiyou Zhao , Hao Wang
发明人： Houfei Chen , Shiyou Zhao , Hao Wang
IPC分类号： H05K1/03
CPC分类号： H05K1/0218 , H05K1/0233 , H05K3/403 , H05K2201/086
摘要： The invention comprises an improved PCB board design having particular utility for high frequency application, and especially useful to alleviate the problem of electromagnetic disturbance of signals switching through power and ground planes. In one embodiment, the PCB contains a magnetically loaded absorbing boundary to absorb the EM disturbances and keep them from resonating inside the cavity between the power and ground planes. The boundary is preferably placed at an edge or edges of the PCB, where it is unlikely to affect any other signals on the PCB. Exemplary materials for the boundary have a magnetic loss tangent of 1.0 to 1.5 with an attenuation constant of −20 dB/cm over frequencies of interest. Depending on whether the boundary material is solid or non-solid, it may be adhered to the edges of the PCB, or may be applied to the edge and cured. It is preferable that the boundary material span through substantially the entire height of the dielectric cavity between the power and ground planes to best absorb the electromagnetic disturbances.
摘要翻译：本发明包括一种改进的PCB板设计，具有高频应用的特殊用途，特别适用于减轻通过电源和接地层切换的信号的电磁干扰问题。在一个实施例中，印刷电路板包含一个吸磁边界，用于吸收电磁干扰并保持它们在电源和接地层之间的空腔内不会谐振。边界优选放置在PCB的边缘或边缘处，其不太可能影响PCB上的任何其他信号。用于边界的示例性材料具有1.0至1.5的磁损耗正切，在感兴趣的频率上的衰减常数为-20dB / cm。根据边界材料是固体还是非固体，它可以粘附到PCB的边缘，或者可以施加到边缘并固化。优选的是，边界材料跨越电源层和接地层之间的电介质的大致整个高度，以最好地吸收电磁干扰。

7. 发明申请

US20070193775A1 Impedance matching via structure for high-speed printed circuit boards and method of determining same 审中-公开
标题翻译：用于高速印刷电路板的阻抗匹配通孔结构及其确定方法
公开(公告)号：US20070193775A1
公开(公告)日：2007-08-23
申请号：US11357544
申请日：2006-02-17
申请人： Houfei Chen , Shiyou Zhao
发明人： Houfei Chen , Shiyou Zhao
IPC分类号： H05K1/11 , H01R12/04
CPC分类号： H05K1/0251 , H05K1/0222 , H05K1/115 , H05K3/429 , H05K2201/09809
摘要： An impedance matching conductive via structure that is effectively constructed by selecting an outer conductor and an inner conductor diameter through analytical calculation or numerical simulation, such that impedance of the conductive via structure is matched to the impedance of the conductive signal traces of a printed circuit board. The conductive via structure comprises a conductive barrel that either connects to multiple ground planes or to multiple powers planes and serves as the outer conductor for a coaxial structure that provides a current return path and a matched impedance path of via transition, thus improving the signal transition and reducing signal reflection due to via discontinuity. Moreover, the conductive barrel of the conductive via structure also reduces radiation loss through a parallel plane structure and suppresses coupling between neighboring vias as the energy escaping through the conductive barrel and radiating to other vias is minimized.
摘要翻译：阻抗匹配导电通孔结构，其通过分析计算或数值模拟选择外部导体和内部导体直径有效地构成，使得导电通孔结构的阻抗与印刷电路板的导电信号迹线的阻抗匹配。导电通孔结构包括导电筒，其连接到多个接地平面或多个功率平面，并且用作提供电流返回路径和通孔转换的匹配阻抗路径的同轴结构的外导体，从而改善信号转换并减少由于通孔不连续性引起的信号反射。此外，导电通孔结构的导电筒还通过平行平面结构降低辐射损耗并且抑制相邻通孔之间的耦合，因为通过导电筒逃逸的能量和辐射到其它通孔被最小化。

8. 发明申请

US20060237227A1 Circuit board via structure for high speed signaling 审中-公开
标题翻译：电路板通孔结构，用于高速信号
公开(公告)号：US20060237227A1
公开(公告)日：2006-10-26
申请号：US11114420
申请日：2005-04-26
申请人： Shiyou Zhao , Houfei Chen , Hao Wang
发明人： Shiyou Zhao , Houfei Chen , Hao Wang
IPC分类号： H05K1/11
CPC分类号： H05K3/429 , H05K1/0222 , H05K1/115 , H05K1/162 , H05K3/10 , H05K3/42 , H05K2201/09809 , Y10T29/49155 , Y10T29/49156 , Y10T29/4916 , Y10T29/49163 , Y10T29/49165 , Y10T29/49167
摘要： One embodiment of the invention comprises an improved via structure for use in a printed circuit board (PCB), and method for fabricating the same. The via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal plane. To minimize EM disturbance between the power and ground planes, signal loss due to signal return current, and via-to-via coupling, the via is shielded within two concentric cylinders, each coupled to one of the power and ground planes.
摘要翻译：本发明的一个实施例包括用于印刷电路板（PCB）的改进的通孔结构及其制造方法。该通孔允许信号从（PCB）中的一个信号平面传递到另一个信号面，并且这样做会超过信号平面之间的电源和接地平面。为了最小化电源和接地层之间的电磁干扰，由于信号返回电流引起的信号损耗以及通孔到通孔耦合，通孔被屏蔽在两个同心圆柱体中，每个连接到电源和接地层之一。

9. 发明授权

US08508950B2 Substrates, systems, and devices including structures for suppressing power and ground plane noise, and methods for suppressing power and ground plane noise 有权
标题翻译：包括用于抑制电力和接地平面噪声的结构的基板，系统和装置，以及用于抑制电力和接地平面噪声的方法
公开(公告)号：US08508950B2
公开(公告)日：2013-08-13
申请号：US12842637
申请日：2010-07-23
申请人： Houfei Chen , Shiyou Zhao
发明人： Houfei Chen , Shiyou Zhao
IPC分类号： H05K1/18
CPC分类号： H05K1/0216 , G11C5/04 , G11C5/063 , H05K1/0298 , H05K1/162 , H05K2201/09309 , H05K2201/09636 , H05K2201/09981 , H05K2203/0733 , Y10T29/4913 , Y10T29/49155
摘要： Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The at least one noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.
摘要翻译：具有电源和接地层的衬底，例如印刷电路板，包括至少一个噪声抑制结构，其被配置为抑制通过电力平面和接地平面中的至少一个传播的电波。所述至少一个噪声抑制结构可以包括从所述功率平面大致朝向所述接地平面延伸的电力平面延伸部，以及从所述接地平面大致向所述电力平面延伸的接地平面延伸部。接地平面延伸部可以与动力平面延伸部分离距离小于分离动力和接地平面的距离。电子器件组件和系统包括这样的衬底。用于抑制电力平面和接地平面中的至少一个中的噪声的方法包括在电源和接地层之间提供这种噪声抑制结构。

10. 发明授权

US08023293B2 On-die anti-resonance structure for integrated circuit 有权
标题翻译：用于集成电路的片上反共振结构
公开(公告)号：US08023293B2
公开(公告)日：2011-09-20
申请号：US12625090
申请日：2009-11-24
申请人： Houfei Chen
发明人： Houfei Chen
IPC分类号： H02H3/22 , H02M1/14
CPC分类号： G06F1/26 , H01L23/64 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to reduce the output impedance of the power delivery system at the resonance frequency.
摘要翻译：描述了用于降低集成电路组件中芯片封装谐振的影响的结构和方法。采用串联RLC电路来降低功率输送系统在谐振频率下的输出阻抗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式