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1. 发明授权

US07947592B2 Thick metal interconnect with metal pad caps at selective sites and process for making the same 有权
标题翻译：在选择性位置的金属焊盘盖的金属金属互连和制造相同的工艺
公开(公告)号：US07947592B2
公开(公告)日：2011-05-24
申请号：US12012120
申请日：2008-01-31
申请人： Hormazdyar Minocher Dalal , Jagdish Prasad , Hocine Bouzid Ziad
发明人： Hormazdyar Minocher Dalal , Jagdish Prasad , Hocine Bouzid Ziad
IPC分类号： H01L21/44
CPC分类号： C23C14/022 , C23C14/165 , C23C14/584 , C23C18/1605 , C23C18/1651 , C23C18/32 , C23C18/54 , C23C28/321 , C23C28/322 , C23C28/34 , C23C28/345 , C25D5/022 , H01L21/76804 , H01L21/76834 , H01L21/76837 , H01L21/76885 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/03462 , H01L2224/0347 , H01L2224/04042 , H01L2224/05005 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05144 , H01L2224/05147 , H01L2224/05184 , H01L2224/05547 , H01L2224/05548 , H01L2224/05562 , H01L2224/05567 , H01L2224/05568 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48465 , H01L2224/4847 , H01L2224/48599 , H01L2224/48644 , H01L2224/48647 , H01L2224/48699 , H01L2224/48744 , H01L2224/48747 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/04941 , H01L2924/1305 , H01L2924/14 , H01L2924/1461 , H01L2924/00014 , H01L2924/01022 , H01L2924/00012 , H01L2224/13147 , H01L2224/13144 , H01L2924/00 , H01L2924/00015 , H01L2224/05552
摘要： The present invention relates to a high power IC (Integrated Circuit) semiconductor device and process for making same. More particularly, the invention encompasses a high conductivity or low resistance metal stack to reduce the device R-on which is stable at high temperatures while in contact with a thick aluminum wire-bond that is required for high current carrying capability and is mechanically stable against vibration during use, and process thereof. The invention further discloses a thick metal interconnect with metal pad caps at selective sites, and process for making the same.
摘要翻译：本发明涉及一种高功率IC（集成电路）半导体器件及其制造方法。更具体地，本发明包括高导电性或低电阻金属叠层，以减少在高温下稳定的器件R-on，同时与用于高电流承载能力所需的厚铝线接合并且机械稳定地抵抗使用过程中的振动及其过程。本发明还公开了一种在选择性位置具有金属垫帽的厚金属互连及其制造方法。

2. 发明授权

US06597067B1 Self-aligned, lateral diffusion barrier in metal lines to eliminate electromigration 失效
标题翻译：金属线中的自对准横向扩散阻挡层，以消除电迁移
公开(公告)号：US06597067B1
公开(公告)日：2003-07-22
申请号：US08839843
申请日：1997-04-17
申请人： Glenn Allen Biery , Daniel Mark Boyne , Hormazdyar Minocher Dalal , H. Daniel Schnurmann
发明人： Glenn Allen Biery , Daniel Mark Boyne , Hormazdyar Minocher Dalal , H. Daniel Schnurmann
IPC分类号： H01L2348
CPC分类号： H01L23/53257 , H01L23/5283 , H01L23/53214 , H01L2924/0002 , Y10S257/915 , H01L2924/00
摘要： An interconnection wiring structure in an integrated circuit chip designed to eliminate electromigration. The structure includes segments of aluminum interspersed with segments of refractory metal, wherein each aluminum segment is followed by a segment of refractory metal. The aluminum and refractory metal segments are aligned with respect to each other to ensure electrical continuity and to force the electrical current to sequentially cross the aluminum and the refractory metal segments. The above structure can be advantageously enhanced by adding an underlayer, an overlayer or both, all of which are made of refractory metal. The interconnection wire structure described above can be expanded to include vias or studs linking interconnection lines placed at different levels of the IC chip.
摘要翻译：设计用于消除电迁移的集成电路芯片中的互连布线结构。该结构包括散布有难熔金属片段的铝片段，其中每个铝片段之后是难熔金属片段。铝和难熔金属段相对于彼此对准以确保电连续性并且迫使电流顺序地交叉铝和难熔金属段。通过添加由难熔金属制成的底层，覆盖层或两者均可有利地提高上述结构。上述互连线结构可以扩展为包括连接放置在IC芯片的不同级别的互连线的通孔或螺柱。

3. 发明授权

US06344234B1 Method for forming reflowed solder ball with low melting point metal cap 失效
标题翻译：用低熔点金属帽形成回流焊球的方法
公开(公告)号：US06344234B1
公开(公告)日：2002-02-05
申请号：US08476475
申请日：1995-06-07
申请人： Hormazdyar Minocher Dalal , Alexis Bitaillou , Kenneth Michael Fallon , Gene Joseph Gaudenzi , Kenneth Robert Herman , Frederic Pierre , Georges Robert
发明人： Hormazdyar Minocher Dalal , Alexis Bitaillou , Kenneth Michael Fallon , Gene Joseph Gaudenzi , Kenneth Robert Herman , Frederic Pierre , Georges Robert
IPC分类号： B05D512
CPC分类号： H01L24/12 , H01L21/4853 , H01L23/49816 , H01L24/11 , H01L2224/0401 , H01L2224/05171 , H01L2224/05184 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/05671 , H01L2224/11472 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/136 , H01L2224/13609 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H05K3/3436 , H05K3/3463 , H05K2201/10992 , H05K2203/0435 , Y02P70/613 , Y10T29/49144 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/013
摘要： A method and structure for a solder interconnection, using solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate is disclosed. After a solder ball has been formed using standard methods it is reflowed to give the solder ball a smooth surface. A layer of low melting point metal, such as, bismuth, indium or tin, preferably, pure tin, is deposited on the top of the solder balls. This structure results in localizing of the eutectic alloy, formed upon subsequent low temperature joining cycle, to the top of the high melting solder ball even after multiple low temperature reflow cycles. This method does not need tinning of the substrate to which the chip is to be joined, which makes this method economical. It has also been noticed that whenever temperature is raised slightly above the eutectic temperature, the structure always forms a liquid fillet around the joint with copper wires. This liquid fillet formation results in substantial thermal fatigue life improvement for reduced stress at interface; and secondly, provides an easy means to remove chip for the purpose of chip burn-in, replacement or field repairs.
摘要翻译：公开了一种用于焊接互连的方法和结构，其使用用于将低温芯片附接到任何更高级别的封装衬底的焊球。在使用标准方法形成焊球后，回流焊锡球表面光滑。一层低熔点金属，例如铋，铟或锡，优选纯锡，沉积在焊料球的顶部。这种结构导致即使在多个低温回流循环之后，在随后的低温接合循环中形成的共晶合金也定位到高熔点焊球的顶部。该方法不需要对芯片要连接的基板进行镀锡，这使得该方法成本低廉。还注意到，当温度升高到略高于共熔温度的情况下，结构总是用铜线在接头周围形成液体圆角。这种液体圆角形成导致显着的热疲劳寿命改善以减少界面处的应力; 其次，为了芯片烧录，更换或现场维修的目的，提供了一种便于拆卸芯片的方法。

4. 发明授权

US06259159B1 Reflowed solder ball with low melting point metal cap 失效
标题翻译：具有低熔点金属帽的回流焊球
公开(公告)号：US06259159B1
公开(公告)日：2001-07-10
申请号：US08794982
申请日：1997-01-30
申请人： Hormazdyar Minocher Dalal , Alexis Bitaillou , Kenneth Michael Fallon , Gene Jospeh Gaudenzi , Kenneth Robert Herman , Frederic Pierre , Georges Robert
发明人： Hormazdyar Minocher Dalal , Alexis Bitaillou , Kenneth Michael Fallon , Gene Jospeh Gaudenzi , Kenneth Robert Herman , Frederic Pierre , Georges Robert
IPC分类号： H01L2348
CPC分类号： H01L24/12 , H01L21/0331 , H01L21/4853 , H01L23/49816 , H01L24/11 , H01L2224/0401 , H01L2224/05171 , H01L2224/05184 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/05671 , H01L2224/1147 , H01L2224/11472 , H01L2224/11902 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/136 , H01L2224/13609 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H05K3/143 , H05K3/3436 , H05K3/3463 , H05K2201/10992 , H05K2203/043 , Y02P70/613 , H01L2924/00014 , H01L2224/13099 , H01L2224/29099 , H01L2924/00 , H01L2924/013
摘要： A method and structure for a solder interconnection, using solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate is disclosed. After a solder ball has been formed using standard methods it is reflowed to give the solder ball a smooth surface. A layer of low melting point metal, such as, bismuth, indium or tin, preferably, pure tin, is deposited on the top of the solder balls. This structure results in localizing of the eutectic alloy, formed upon subsequent low temperature joining cycle, to the top of the high melting solder ball even after multiple low temperature reflow cycles. This method does not need tinning of the substrate to which the chip is to be joined, which makes this method economical. It has also been noticed that whenever temperature is raised slightly above the eutectic temperature, the structure always forms a liquid fillet around the joint with copper wires. This liquid fillet formation results in substantial thermal fatigue life improvement for reduced stress at interface; and secondly, provides an easy means to remove chip for the purpose of chip burn-in, replacement or field repairs.
摘要翻译：公开了一种用于焊接互连的方法和结构，其使用用于将低温芯片附接到任何更高级别的封装衬底的焊球。在使用标准方法形成焊球后，回流焊锡球表面光滑。一层低熔点金属，例如铋，铟或锡，优选纯锡，沉积在焊料球的顶部。这种结构导致即使在多个低温回流循环之后，在随后的低温接合循环中形成的共晶合金也定位到高熔点焊球的顶部。该方法不需要对芯片要连接的基板进行镀锡，这使得该方法成本低廉。还注意到，当温度升高到略高于共熔温度的情况下，结构总是用铜线在接头周围形成液体圆角。这种液体圆角形成导致显着的热疲劳寿命改善以减少界面处的应力; 其次，为了芯片烧录，更换或现场维修的目的，提供了一种便于拆卸芯片的方法。

5. 发明授权

US6051273A Method for forming features upon a substrate 失效
标题翻译：在基底上形成特征的方法
公开(公告)号：US6051273A
公开(公告)日：2000-04-18
申请号：US972184
申请日：1997-11-18
申请人： Hormazdyar Minocher Dalal , Gene Joseph Gaudenzi , Frederic Robert Pierre , Georges Henri Robert
发明人： Hormazdyar Minocher Dalal , Gene Joseph Gaudenzi , Frederic Robert Pierre , Georges Henri Robert
IPC分类号： B23K3/06 , B05D5/12
CPC分类号： B23K3/0623
摘要： A material deposition process is disclosed in which apertures of a contact mask used therein have a constricted opening terminating in a `knife edge` in a sidewall thereof near the top mask side, especially within the top 25% of the mask thickness above the substrate. A process is disclosed in which the mask, in addition, has apertures which have larger dimension lower openings on a bottom side of the mask contacting the substrate than constricted openings near the top side of the mask. Single solder bump and "bump on bump" over BLM (ball limiting metallurgy) processes are disclosed which utilize such contact mask to reduce the damage and detaching of such features during processing and subsequent handling.
摘要翻译：公开了一种材料沉积工艺，其中在其中使用的接触掩模的孔具有在靠近顶部掩模侧的侧壁中的“刀刃”中终止的收缩开口，特别是在衬底上方的掩模厚度的顶部25％之内。公开了一种方法，其中掩模另外具有孔，其具有在与掩模接触的底部的较大尺寸的下部开口，而不是靠近掩模顶侧的收缩开口。公开了在BLM（球限制冶金）方法中的单个焊料凸块和“凸起凸起”工艺，其利用这种接触掩模在处理和随后的处理期间减少这些特征的损坏和分离。

6. 发明授权

US5976970A Method of making and laterally filling key hole structure for ultra fine pitch conductor lines 失效
标题翻译：超细间距导线的关键孔结构的制作和横向填充方法
公开(公告)号：US5976970A
公开(公告)日：1999-11-02
申请号：US626764
申请日：1996-03-29
申请人： Hormazdyar Minocher Dalal , Hazara Singh Rathore
发明人： Hormazdyar Minocher Dalal , Hazara Singh Rathore
IPC分类号： H01L21/768 , H01L23/532 , H01L21/283
CPC分类号： H01L21/76877 , H01L23/53233 , H01L2924/0002
摘要： A method of forming electrical conductors having sub-half-micron geometries and using a high yield process is described. Trenches provided with an overhang are positioned where a metal interconnection is to be formed. A composite insulator layer is deposited and is followed by laterally filling with metal the trench under the overhang. Excess metal is then chem-mech polished. Only the non-crucial neck of the metal wiring is left exposed during polishing. Since spacing between the exposed metal lines is increased, it requires longer distances for the metal to smear and cause unwanted shorts. Three methods are described to laterally fill the trenches under the overhang. A first method describes the process parameters to achieve lateral deposition by high surface mobility and low sticking coefficient. A second method teaches a technique of inducing micro-creep to laterally fill the trenches under the overhang. A third method shows metal layered structures where volume expansion takes place upon phase transformation.
摘要翻译：描述了形成具有亚半微米几何形状并且使用高产量工艺的电导体的方法。设置有突出端的沟槽位于要形成金属互连的位置。沉积复合绝缘体层，然后用金属横向填充突出部下方的沟槽。然后过量的金属被化学磨光。只有金属布线的非关键颈部在抛光过程中才会露出。由于暴露的金属线之间的间距增加，所以需要更长的距离来使金属涂抹并引起不想要的短路。描述了三种方法来横向填充突出部下方的沟槽。第一种方法描述了通过高表面迁移率和低粘附系数实现横向沉积的工艺参数。第二种方法教导了一种诱导微蠕变以横向填充突出部下方的沟槽的技术。第三种方法显示了在相变时发生体积膨胀的金属层状结构。

7. 发明授权

US07800239B2 Thick metal interconnect with metal pad caps at selective sites and process for making the same 有权
标题翻译：在选择性位置的金属焊盘盖的金属金属互连和制造相同的工艺
公开(公告)号：US07800239B2
公开(公告)日：2010-09-21
申请号：US12012121
申请日：2008-01-31
申请人： Hormazdyar Minocher Dalal , Jagdish Prasad , Hocine Bouzid Ziad
发明人： Hormazdyar Minocher Dalal , Jagdish Prasad , Hocine Bouzid Ziad
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： C23C14/022 , C23C14/165 , C23C14/584 , C23C18/1605 , C23C18/1651 , C23C18/32 , C23C18/54 , C23C28/321 , C23C28/322 , C23C28/34 , C23C28/345 , C25D5/022 , H01L21/76804 , H01L21/76834 , H01L21/76837 , H01L21/76885 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/03462 , H01L2224/0347 , H01L2224/04042 , H01L2224/05005 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05144 , H01L2224/05147 , H01L2224/05184 , H01L2224/05547 , H01L2224/05548 , H01L2224/05562 , H01L2224/05567 , H01L2224/05568 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48465 , H01L2224/4847 , H01L2224/48599 , H01L2224/48644 , H01L2224/48647 , H01L2224/48699 , H01L2224/48744 , H01L2224/48747 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/04941 , H01L2924/1305 , H01L2924/14 , H01L2924/1461 , H01L2924/00014 , H01L2924/01022 , H01L2924/00012 , H01L2224/13147 , H01L2224/13144 , H01L2924/00 , H01L2924/00015 , H01L2224/05552
摘要： The present invention relates to a high power IC (Integrated Circuit) semiconductor device and process for making same. More particularly, the invention encompasses a high conductivity or low resistance metal stack to reduce the device R-on which is stable at high temperatures while in contact with a thick aluminum wire-bond that is required for high current carrying capability and is mechanically stable against vibration during use, and process thereof. The invention further discloses a thick metal interconnect with metal pad caps at selective sites, and process for making the same.
摘要翻译：本发明涉及一种高功率IC（集成电路）半导体器件及其制造方法。更具体地，本发明包括高导电性或低电阻金属叠层，以减少在高温下稳定的器件R-on，同时与用于高电流承载能力所需的厚铝线接合并且机械稳定地抵抗使用过程中的振动及其过程。本发明还公开了一种在选择性位置具有金属垫帽的厚金属互连及其制造方法。

8. 发明申请

US20090152725A1 Thick metal interconnect with metal pad caps at selective sites and process for making the same 有权
标题翻译：在选择性位置的金属焊盘盖的金属金属互连和制造相同的工艺
公开(公告)号：US20090152725A1
公开(公告)日：2009-06-18
申请号：US12012121
申请日：2008-01-31
申请人： Hormazdyar Minocher Dalal , Jagdish Prasad , Hocine Bouzid Ziad
发明人： Hormazdyar Minocher Dalal , Jagdish Prasad , Hocine Bouzid Ziad
IPC分类号： H01L23/49
CPC分类号： C23C14/022 , C23C14/165 , C23C14/584 , C23C18/1605 , C23C18/1651 , C23C18/32 , C23C18/54 , C23C28/321 , C23C28/322 , C23C28/34 , C23C28/345 , C25D5/022 , H01L21/76804 , H01L21/76834 , H01L21/76837 , H01L21/76885 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/03462 , H01L2224/0347 , H01L2224/04042 , H01L2224/05005 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05144 , H01L2224/05147 , H01L2224/05184 , H01L2224/05547 , H01L2224/05548 , H01L2224/05562 , H01L2224/05567 , H01L2224/05568 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48465 , H01L2224/4847 , H01L2224/48599 , H01L2224/48644 , H01L2224/48647 , H01L2224/48699 , H01L2224/48744 , H01L2224/48747 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/04941 , H01L2924/1305 , H01L2924/14 , H01L2924/1461 , H01L2924/00014 , H01L2924/01022 , H01L2924/00012 , H01L2224/13147 , H01L2224/13144 , H01L2924/00 , H01L2924/00015 , H01L2224/05552
摘要： The present invention relates to a high power IC (Integrated Circuit) semiconductor device and process for making same. More particularly, the invention encompasses a high conductivity or low resistance metal stack to reduce the device R-on which is stable at high temperatures while in contact with a thick aluminum wire-bond that is required for high current carrying capability and is mechanically stable against vibration during use, and process thereof. The invention further discloses a thick metal interconnect with metal pad caps at selective sites, and process for making the same.
摘要翻译：本发明涉及一种高功率IC（集成电路）半导体器件及其制造方法。更具体地，本发明包括高导电性或低电阻金属叠层，以减少在高温下稳定的器件R-on，同时与用于高电流承载能力所需的厚铝线接合并且机械稳定地抵抗使用过程中的振动及其过程。本发明还公开了一种在选择性位置具有金属垫帽的厚金属互连及其制造方法。

9. 发明授权

US06734090B2 Method of making an edge seal for a semiconductor device 失效
标题翻译：制造半导体器件的边缘密封的方法
公开(公告)号：US06734090B2
公开(公告)日：2004-05-11
申请号：US10078861
申请日：2002-02-20
申请人： Birendra N. Agarwala , Hormazdyar Minocher Dalal , Eric G. Liniger , Diana Llera-Hurlburt , Du Binh Nguyen , Richard W. Procter , Hazara Singh Rathore , Chunyan E. Tian , Brett H. Engel
发明人： Birendra N. Agarwala , Hormazdyar Minocher Dalal , Eric G. Liniger , Diana Llera-Hurlburt , Du Binh Nguyen , Richard W. Procter , Hazara Singh Rathore , Chunyan E. Tian , Brett H. Engel
IPC分类号： H01L2144
CPC分类号： H01L21/76831 , H01L21/76801 , H01L21/76807
摘要： An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.
摘要翻译：围绕集成电路器件周边的边缘密封，其环境地保护铜电路免受在切割期间可能在低k层间电介质中形成的裂纹。边缘密封件基本上构成在集成电路器件周边附近的铜电路和低k层间电介质之间的电介质壁。电介质壁是与低k层间电介质不同的材料。

10. 发明授权

US5922496A Selective deposition mask and method for making the same 失效
标题翻译：选择性沉积掩模及其制作方法
公开(公告)号：US5922496A
公开(公告)日：1999-07-13
申请号：US972183
申请日：1997-11-18
申请人： Hormazdyar Minocher Dalal , Gene Joseph Gaudenzi , Frederic Robert Pierre , Georges Henri Robert
发明人： Hormazdyar Minocher Dalal , Gene Joseph Gaudenzi , Frederic Robert Pierre , Georges Henri Robert
IPC分类号： G03F7/00 , G03F7/40 , H01L21/60 , G03F9/00
CPC分类号： G03F7/40 , H01L24/11 , G03F7/00 , H01L2224/11005 , H01L2224/11472 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14
摘要： A material deposition contact mask is disclosed in which apertures formed therein have a larger dimension in lower openings in a bottom side of the mask contacting the substrate than in constricted openings located near the top side of the mask. Apertures of the contact mask have knife edges located within the upper sidewalls thereof, e.g. within the top 25% of the mask thickness above the substrate. A mask is disclosed which, in addition, is thermally compensated to the substrate temperature at which the deposition is performed. Methods for fabricating the mask by differential etching are disclosed.
摘要翻译：公开了一种材料沉积接触掩模，其中形成在其中的孔在与掩模接触的掩模的底侧中的下开口中具有比在位于掩模的顶侧附近的收缩开口中更大的尺寸。接触掩模的孔径具有位于其上侧壁内的刀刃，例如，在衬底上方的掩模厚度的前25％内。公开了一种掩模，其另外被热补偿到执行沉积的衬底温度。公开了通过差分蚀刻来制造掩模的方法。

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