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1. 发明授权

US07151798B2 Method for motion estimation using a low-bit edge image 有权
标题翻译：使用低位边缘图像的运动估计方法
公开(公告)号：US07151798B2
公开(公告)日：2006-12-19
申请号：US10283863
申请日：2002-10-29
申请人： Hongyi Chen , Xiaohai Qiu
发明人： Hongyi Chen , Xiaohai Qiu
IPC分类号： H04B1/66 , G06K9/40
CPC分类号： H04N19/51 , H04N5/145
摘要： The invention provides a method for a motion estimation algorithm. The motion estimation algorithm using low bit resolution integrated edge image instead of luminance image to obtain difference block with small AC coefficients, edge image created by filters is employed to improve encoding quality, on the other hand, operation cost is reduced to low bit resolution. The invention also provides a method for a motion estimation algorithm with a new algorithm using low-bit resolution oriented edge image. Using low-bit resolution oriented edge in motion estimation can result in flatter image blocks which is in demanded by texture-compress unit (such as DCT), as a result, the encoding efficiency is improved, and the operation load is reduced by low-bit resolution.
摘要翻译：本发明提供一种运动估计算法的方法。使用低位分辨率集成边缘图像而不是亮度图像的运动估计算法来获得具有小AC系数的差分块，由滤波器创建的边缘图像用于提高编码质量，另一方面，操作成本降低到低位分辨率。本发明还提供了一种使用低位分辨率定向边缘图像的新算法的运动估计算法。在运动估计中使用低位分辨率的边缘可能导致纹理压缩单元（如DCT）所要求的较平坦的图像块，结果提高了编码效率，并且降低了运算负载，位分辨率。

2. 发明授权

US5966040A CMOS current-mode four-quadrant analog multiplier 失效
标题翻译： CMOS电流模式四象限模拟乘法器
公开(公告)号：US5966040A
公开(公告)日：1999-10-12
申请号：US938747
申请日：1997-09-26
申请人： Weixin Gai , Hongyi Chen
发明人： Weixin Gai , Hongyi Chen
IPC分类号： G06G7/164 , G06F7/44
CPC分类号： G06G7/164
摘要： A current-mode four-quadrant analog multiplier is provided, which is constructed based on CMOS (complementary metal-oxide semiconductor) technology, capable of generating an output current signal which is proportional in magnitude to the product of two input current signals. This current-mode analog multiplier is designed based on the translinear circuit principle. The current-mode analog multiplier has high precision, wide current dynamic range, and is insensitive to temperature and process, suitable for use in VLSI implementation of many analog circuits and systems, such as fuzzy logic controllers and analog neural networks.
摘要翻译：提供了基于CMOS（互补金属氧化物半导体）技术构建的电流模式四象限模拟乘法器，其能够产生与两个输入电流信号的乘积成比例的输出电流信号。该电流模式模拟乘法器是基于跨线电路原理设计的。电流模式模拟乘法器具有高精度，宽电流动态范围，对温度和过程不敏感，适用于许多模拟电路和系统（如模糊逻辑控制器和模拟神经网络）的VLSI实现。

3. 发明授权

US06424986B1 Architecture of discrete wavelet transformation 有权
标题翻译：离散小波变换的架构
公开(公告)号：US06424986B1
公开(公告)日：2002-07-23
申请号：US09321664
申请日：1999-05-28
申请人： Yongming Li , Hongyi Chen , Xiaodong Wu
发明人： Yongming Li , Hongyi Chen , Xiaodong Wu
IPC分类号： G06F1714
CPC分类号： G06F17/148
摘要： A VLSI wavelet transform (WT) architecture suitable for use in a discrete wavelet transform (DWT) or a discrete wavelet packet transform (DWPT). The WT architecture has a multiplier; an accumulator; at least two address generators that has a first address generator and a second address generator; a control unit; a memory of result that stores computation results; and a memory of table, which pre-stores all possible weights, each of which weights is a product of some specified filter coefficients for performing a DWT/DWPT with parameters of decomposition level, length of data segment, and filter length. The first address generator and the control unit receive data input, the control unit exports control signals to multiplier, accumulator, second address generator, and memory of table. The memory of the table also receives outputs from the first address generator and the second address generator to select the desired weights of the filter coefficients, which are sent to the multiplier to obtain a product with the data input. The product is sent to the accumulator to add into a corresponding sum, and the memory of result receives the corresponding sum and an address output of the second address generator to address the received corresponding sum, in which when all of the data input in the DWT/DWPT are completely inputted, each the corresponding sum is an end result of the DWT/DWPT.
摘要翻译：适用于离散小波变换（DWT）或离散小波包变换（DWPT）的VLSI小波变换（WT）架构。 WT架构有一个乘数; 蓄能器至少两个具有第一地址发生器和第二地址发生器的地址发生器; 一个控制单元; 存储计算结果的结果记忆; 和表的存储器，其预存储所有可能的权重，其中每个权重是用于执行具有分解级别的参数，数据段的长度和过滤器长度的DWT / DWPT的一些指定的滤波器系数的乘积。第一地址发生器和控制单元接收数据输入，控制单元将控制信号输出到乘法器，累加器，第二地址发生器和表的存储器。表的存储器还接收来自第一地址发生器和第二地址发生器的输出，以选择滤波器系数的期望权重，这些权重被发送到乘法器以获得具有数据输入的乘积。产品被发送到累加器以加入相应的和，并且结果的存储器接收第二地址发生器的相应的和和地址输出以寻址接收到的对应的和，其中当DWT中输入的所有数据 / DWPT完全输入，每个相应的和是DWT / DWPT的最终结果。

4. 发明授权

US6061706A Systolic linear-array modular multiplier with pipeline processing elements 失效
标题翻译：收缩线性阵列模拟乘法器与流水线处理元件
公开(公告)号：US6061706A
公开(公告)日：2000-05-09
申请号：US949036
申请日：1997-10-10
申请人： Weixin Gai , Hongyi Chen
发明人： Weixin Gai , Hongyi Chen
IPC分类号： G06F7/72 , G06F7/38
CPC分类号： G06F7/728 , G06F2207/3884
摘要： A systolic linear-array modular multiplier is provided, which can perform the modular multiplication algorithm of P. L. Montgomery more efficiently. The total execution time for n-bit modular multiplication is 2n+11 cycles. The modular multiplier includes a linear array of processing elements which is constructed based on a pipeline architecture that can reduce the computation procedure by one clock period. Each of the processing elements is simple in structure, which is composed of four full adders and fourteen flip-flops. For n-bit modular multiplication, a total number of 46n+184 gates is required, which is substantially less as compared to the prior art, so that manufacturing cost of the modular multiplier can be significantly reduced. These features make the modular multiplier suitable for use in VLSI implementation of modular exponentiation which is the kernel computation in many public-key cryptosystems, such as the RSA (Rivest-Shamir-Adleman) system. With the 0.8 .mu.m CMOS technology, a clock signal up to 180 MHz can be used. In average, for n-bit modular multiplication, the encryption speed can reach 116 Kbit/s (kilobits per second), which is substantially twice that achieved by the prior art.
摘要翻译：提供了一种收缩线性阵列模乘法，可以更有效地执行P.L. Montgomery的模乘法。 n位模乘的总执行时间为2n + 11个周期。模数乘法器包括一个基于流水线结构构造的处理元件的线性阵列，可以将计算过程减少一个时钟周期。每个处理元件的结构简单，由四个全加器和十四个触发器组成。对于n位模乘法，需要总共46n + 184个门，这与现有技术相比要小得多，因此可以大大减少模乘器的制造成本。这些特征使得模块乘法器适用于VLSI实现模幂运算，这是多指令密码系统中的核心计算，如RSA（Rivest-Shamir-Adleman）系统。采用0.8微米CMOS技术，可以使用高达180 MHz的时钟信号。平均来说，对于n位模乘，加密速度可以达到116Kbit / s（千比特每秒），这是现有技术实现的两倍。

5. 发明授权

US5721595A Motion estimation block matching process and apparatus for video image processing 失效
标题翻译：运动估计块匹配过程和视频图像处理装置
公开(公告)号：US5721595A
公开(公告)日：1998-02-24
申请号：US666986
申请日：1996-06-19
申请人： Hongyi Chen , Qingming Shu
发明人： Hongyi Chen , Qingming Shu
IPC分类号： H04N7/26 , H04N7/32
CPC分类号： H04N19/51
摘要： A process for obtaining a motion vector for motion estimation used in a video image analysis, utilizing a block matching algorithm, which has the effect of reducing the computational load that is placed on the hardware logic used for implementation of the process. In a process of obtaining the absolute error value for the compared image block, a preliminary comparison is performed for every processed pixel in the image block to determine if the set minimum value of the absolute error function represented by a motionless tolerance constant is achieved. It is not necessary to obtain every actual value of the absolute error function. The block matching scheme of providing motion estimation enables hardware implementing the process to discontinue processing if the desired motion vector is selected prior to all image blocks being compared.
摘要翻译：一种用于获得在视频图像分析中使用的用于运动估计的运动矢量的过程，利用块匹配算法，其具有减少放置在用于实现该过程的硬件逻辑上的计算负荷。在获得比较图像块的绝对误差值的处理中，对图像块中的每个处理像素执行初步比较，以确定是否实现由静止公差常数表示的绝对误差函数的设定最小值。没有必要获得绝对误差函数的每个实际值。提供运动估计的块匹配方案使得硬件实现该过程以在所有图像块被比较之前选择期望的运动矢量以停止处理。

6. 发明授权

US5652625A Multi-stage pipeline architecture for motion estimation block matching 失效
标题翻译：用于运动估计块匹配的多级流水线架构
公开(公告)号：US5652625A
公开(公告)日：1997-07-29
申请号：US666987
申请日：1996-06-19
申请人： Hongyi Chen , Qingming Shu
发明人： Hongyi Chen , Qingming Shu
IPC分类号： G06T7/20 , H04N5/14 , H04N7/26 , H04N7/32
CPC分类号： H04N5/145 , G06T7/2013 , H04N19/51 , G06T2200/28 , G06T2207/10016
摘要： An apparatus for implementing motion estimation block matching for video image processing. The apparatus receives pixel data of original and compared image blocks for comparison, to obtain an image motion vector. The apparatus has a multi-stage pipelined tree-architecture that includes a computation stage, a summation section, an accumulation stage, and a minimum value evaluation stage. The computation stage includes 2.sup.n computation members for producing a difference error value and a sign bit of the compared image blocks. The summation section coupled at the pipelined stage next to the computation stage, includes a series of summation stages for producing an absolute error value of the compared image blocks. A following accumulation stage adds an output of the single adder means of the last summation stage and a last un-added sign bit, for producing a sum. A last minimum value evaluator evaluates and generates the minimum of the output of the accumulation stage, as the motion vector for the implementation of motion estimation block matching for video image processing. Only a single adder is required in each of the computation members to reduce both the complexity and the processing delay for increased performance.
摘要翻译：一种用于实现用于视频图像处理的运动估计块匹配的装置。该装置接收用于比较的原始和比较图像块的像素数据，以获得图像运动矢量。该装置具有多级流水线树结构，其包括计算阶段，求和部分，累积阶段和最小值评估阶段。计算阶段包括用于产生差异误差值的2n个计算构件和比较图像块的符号位。耦合在计算阶段旁边的流水线级的求和部分包括用于产生比较图像块的绝对误差值的一系列求和级。以下累加阶段将最后一个加法阶段的单个加法器装置的输出和最后一个未加上的符号位相加，以产生一个和。最后一个最小值评估器评估并产生累积阶段的输出的最小值，作为用于执行视频图像处理的运动估计块匹配的运动矢量。在每个计算构件中仅需要单个加法器，以减少复杂性和处理延迟以提高性能。

7. 发明授权

US6101523A Method and apparatus for controlling calculation error 失效
标题翻译：用于控制计算误差的方法和装置
公开(公告)号：US6101523A
公开(公告)日：2000-08-08
申请号：US81006
申请日：1998-05-19
申请人： Hongyi Chen , Zhiqiang Zeng
发明人： Hongyi Chen , Zhiqiang Zeng
IPC分类号： G06F7/50 , G06F7/505 , H04N7/26 , H04N7/30 , G06F11/00 , G06F17/14
CPC分类号： G06F7/505 , H04N19/45 , H04N19/60 , G06F7/49942
摘要： A method and an apparatus for controlling calculation error produced by the accumulation error due to digit truncation in a non-integer computation. The error is eliminated by controlling the values of LSB, C.sub.in and the addition/subtraction selecting signal as, so that C.sub.in is not necessarily equal to C.sub.in. Considering a even number of cascaded pipelines, C.sub.in in the odd pipelines is set as 0, wherein C.sub.in in the even pipelines is set as 1. The resultant error is thus eliminated mutually by odd and even pipelines.
摘要翻译：一种用于控制由非整数计算中的数字截断引起的累积误差产生的计算误差的方法和装置。通过控制LSB，Cin和加/减选择信号的值来消除误差，使得Cin不一定等于Cin。考虑到偶数级联管道，奇数管线中的Cin被设置为0，其中偶数管线中的Cin被设置为1.因此，奇数和偶数管道相互消除所得到的误差。

8. 发明授权

US5838392A Adaptive block-matching motion estimator with a compression array for use in a video coding system 失效
标题翻译：具有用于视频编码系统的压缩阵列的自适应块匹配运动估计器
公开(公告)号：US5838392A
公开(公告)日：1998-11-17
申请号：US44570
申请日：1998-03-19
申请人： Hongyi Chen , Qingming Shu
发明人： Hongyi Chen , Qingming Shu
IPC分类号： G06T7/20 , H04N5/14 , H04N7/26
CPC分类号： G06T7/2013 , H04N19/43 , H04N19/51 , H04N5/145 , G06T2200/28 , G06T2207/10016
摘要： An adaptive block-matching motion estimator for used in a video coding system wherein the adaptive block-matching motion estimator is less in hardware complexity and latency time and is therefore more cost-effective to implement and higher in performance. This adaptive block-matching motion estimator includes a DS array for processing the pixel data of the current image block and the pixel data of the compared image block to thereby obtain a difference vector and a set of weight bits; a compression array having a first output port for outputting a compressed sum vector and a second output port for outputting an associated compressed carry vector, with the difference vector and the set of weight bits from the DS array along with the compressed sum vector and the associated compressed carry vector being taken as the inputs to the compression array; and a complexity-matching (CM) unit for processing the compressed sum vector and the associated compressed carry vector from the compression array to thereby produce the desired motion vector.
摘要翻译：一种在视频编码系统中使用的自适应块匹配运动估计器，其中自适应块匹配运动估计器在硬件复杂度和延迟时间上较少，因此在性能上实现更高的成本效益。该自适应块匹配运动估计器包括用于处理当前图像块的像素数据和比较图像块的像素数据的DS阵列，从而获得差分矢量和一组权重位; 具有用于输出压缩和矢量的第一输出端口和用于输出相关联的压缩进位向量的第二输出端口的压缩阵列，其中来自DS阵列的差矢量和权重位置集合以及压缩和向量和相关联的将压缩进位矢量作为压缩阵列的输入; 以及用于从压缩阵列处理压缩和矢量和相关联的压缩进位向量的复杂度匹配（CM）单元，从而产生期望的运动矢量。

9. 外观设计

USD927043S1 Night light 有权
公开(公告)号：USD927043S1
公开(公告)日：2021-08-03
申请号：US29716589
申请日：2019-12-10
申请人： Dongdong Tian , Hongyi Chen
设计人： Dongdong Tian , Hongyi Chen

10. 发明申请

US20060161832A1 System and method for generating a cyclic redundancy check 有权
标题翻译：用于生成循环冗余校验的系统和方法
公开(公告)号：US20060161832A1
公开(公告)日：2006-07-20
申请号：US11385962
申请日：2006-03-21
申请人： Hongyi Chen
发明人： Hongyi Chen
IPC分类号： H03M13/00
CPC分类号： H03M13/6516 , H03M13/09
摘要： A Cyclic Redundancy Check (CRC) system comprises N+1 shift registers. N+1 logic gates having first inputs communicate with outputs of corresponding ones of said N+1 shift registers. N+1 programmable registers store a corresponding CRC coefficient of a 3rd to Nth order CRC polynomial key word, wherein N is an integer greater than two. N+1 multiplexers communicate with outputs of corresponding ones of said N+1 logic gates. At least N of said N+1 multiplexers communicate with corresponding ones of at least N of said N+1 programmable registers.
摘要翻译：循环冗余校验（CRC）系统包括N + 1个移位寄存器。具有第一输入的N + 1个逻辑门与所述N + 1个移位寄存器中的相应输入端的输出进行通信。 N + 1个可编程寄存器存储第N次CRC多项式关键字的相应CRC系数，其中N是大于2的整数。 N + 1个复用器与所述N + 1个逻辑门中的相应输出端的输出通信。所述N + 1复用器中的至少N个与所述N + 1个可编程寄存器中的至少N个中的相应的通信。

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