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    • 8. 发明授权
    • Delay locked loop and method of driving delay locked loop
    • 延迟锁定环和驱动延迟锁定环的方法
    • US08264260B2
    • 2012-09-11
    • US12722768
    • 2010-03-12
    • Jae-hong KoHo-Hak RhoPaul Kim
    • Jae-hong KoHo-Hak RhoPaul Kim
    • H03L7/06
    • H03L7/0812H03K5/133H03K5/1565H03K2005/00039H03K2005/00071H03L7/0818H03L7/087
    • Provided are a delay locked loop (DLL) having a pulse width detection circuit and a method of driving the DLL. The DLL includes a pulse width detection circuit and a delay circuit. The pulse width detection circuit receives a reference clock signal, detects a pulse width of the reference clock signal, and outputs the detection result as a pulse width detection result signal. The delay circuit receives and delays the reference clock signal, and outputs the delayed reference clock signal as an output clock signal. The delay circuit receives the pulse width detection result signal from the pulse width detection circuit, and controls a time delay in the reference clock signal in response to the pulse width detection result signal.
    • 提供了具有脉冲宽度检测电路的延迟锁定环(DLL)和驱动DLL的方法。 该DLL包括脉冲宽度检测电路和延迟电路。 脉冲宽度检测电路接收参考时钟信号,检测参考时钟信号的脉冲宽度,并将检测结果作为脉冲宽度检测结果信号输出。 延迟电路接收并延迟参考时钟信号,并输出延迟的参考时钟信号作为输出时钟信号。 延迟电路从脉宽检测电路接收脉宽检测结果信号,并根据脉宽检测结果信号控制参考时钟信号的时间延迟。