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    • 4. 发明申请
    • Method for manufacturing semiconductor device
    • 制造半导体器件的方法
    • US20050186743A1
    • 2005-08-25
    • US11061466
    • 2005-02-22
    • Hiroyuki Utsunomiya
    • Hiroyuki Utsunomiya
    • H01L27/108H01L21/336H01L21/8242
    • H01L27/10876H01L27/10811H01L27/10873H01L29/66537H01L29/66621
    • Provided is a method of manufacturing a semiconductor device capable avoiding occurrence of resist residue on a gate opening portion when forming the gate opening portion finely for injecting an impurity to form an asymmetric transistor during patterning of a gate electrode. The method of manufacturing the semiconductor device, in a case of manufacturing a DRAM (Dynamic Random Access Memory) with a memory cell transistor made up of the asymmetric transistor, performs separately a first gate electrode patterning process for forming a high concentration N-type diffusion region to be electrically connected to a capacitive element via a capacitive contact connect, and a gate second electrode patterning process for forming a high concentration N-type diffusion region to be electrically connected to a bit line via a bit contact.
    • 提供一种制造半导体器件的方法,当在栅电极的图案化期间形成用于注入杂质以形成非对称晶体管的栅极开口部分时,能够避免在栅极开口部分发生抗蚀剂残留。 在制造具有由不对称晶体管构成的存储单元晶体管的DRAM(动态随机存取存储器)的情况下,制造半导体器件的方法分别执行用于形成高浓度N型扩散的第一栅极电极图案化工艺 区域,经由电容性接触连接电连接到电容元件;以及栅极第二电极图案形成工艺,用于形成通过位接触电连接到位线的高浓度N型扩散区域。