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1. 发明申请

US20070033153A1 Disaster prediction system 审中-公开
标题翻译：灾害预测系统
公开(公告)号：US20070033153A1
公开(公告)日：2007-02-08
申请号：US10577473
申请日：2004-10-25
申请人： Ryutaro Yamanaka , Hiroyuki Motozuka , Mitsuru Uesugi
发明人： Ryutaro Yamanaka , Hiroyuki Motozuka , Mitsuru Uesugi
IPC分类号： G06F15/18
CPC分类号： G01V1/008
摘要： A disaster prediction system that provides a plurality of mobile communications apparatuses with a function for detecting abnormal signals that are effective in natural disaster prediction, manages location information for the mobile communications apparatuses and appropriately sets areas of natural disaster prediction, collects a plurality of abnormality detection signals from the mobile communications apparatuses, analyzes these signals per area of prediction, improves the accuracy of natural disaster occurrence prediction, and transmits natural disaster-related information to a plurality of mobile communications apparatuses present in the areas of prediction. In this system, a mobile terminal 200 is equipped with functions for detecting an electromagnetic signal which correlates with earthquake occurrence and which comes from underground and detecting an abnormal electromagnetic signal and a function for locating its present position, a location management apparatus 300 manages location information for a plurality of mobile terminals 200, and an earthquake prediction apparatus 400 appropriately sets the areas of prediction of earthquake occurrence, according to the location management information, and collects a plurality of abnormality detection signals from the mobile terminals 200, generates earthquake-related alert information based on analysis per area of prediction, and transmits that information to the mobile terminals 200.
摘要翻译：一种灾害预测系统，其提供具有检测在自然灾害预测中有效的异常信号的功能的多个移动通信装置，管理移动通信装置的位置信息，适当设定自然灾害预测区域，收集多个异常检测来自移动通信设备的信号，每个预测区域分析这些信号，提高自然灾害发生预测的准确性，并将自然灾害相关信息发送到存在于预测区域中的多个移动通信设备。在该系统中，移动终端200配备有用于检测与地震发生相关并且来自地下的电磁信号的功能，并检测异常电磁信号和定位其当前位置的功能，位置管理装置300管理位置信息对于多个移动终端200，地震预测装置400根据位置管理信息适当地设定地震发生的预测区域，并从移动终端200收集多个异常检测信号，生成地震相关警报基于每个预测区域的分析的信息，并将该信息发送到移动终端200。

2. 发明授权

US08700971B2 Parallel residue arithmetic operation unit and parallel residue arithmetic operating method 有权
标题翻译：并行残差算术运算单元和并行残差运算法
公开(公告)号：US08700971B2
公开(公告)日：2014-04-15
申请号：US12377772
申请日：2007-08-21
申请人： Hiroyuki Motozuka
发明人： Hiroyuki Motozuka
IPC分类号： H03M13/00
CPC分类号： H03M13/091
摘要： A parallel residue arithmetic operation unit is provided to reduce processing delay, and to make an additional multiplier or a residue arithmetic circuit unnecessary, so that a circuit can become small in size. In the parallel residue arithmetic operation unit, a parallel CRC calculation circuit includes input terminals to which input data are divided into a plurality of sub-blocks and the sub-blocks are input in parallel, an initial value generating unit for generating a part CRC corresponding to the forefront of each sub-block as an initial value, a part CRC generating unit for receiving the part CRC corresponding to the forefront of each sub-block as the initial value and sequentially generating a residue part CRC in accordance with a recurrent equation, AND units for calculating logical multiplications of part CRC values, and a cumulative adding unit for cumulatively adding values output from the AND units.
摘要翻译：提供并行残余算术运算单元以减少处理延迟，并且不需要额外的乘法器或残余运算电路，使得电路的尺寸变小。在并行残差算术运算部中，并行CRC计算电路包括输入端子，输入数据被分割成多个子块并且并行输入子块;初始值生成单元，生成部分CRC对应到每个子块的最前面作为初始值，部分CRC生成单元，用于接收与每个子块的最前面相对应的部分CRC作为初始值，并根据循环方程依次生成残差部分CRC， AND单元，用于计算部分CRC值的逻辑乘法，以及累积加法单元，用于累加从AND单元输出的值。

3. 发明申请

US20100169745A1 SOFT OUTPUT DECODER, ITERATIVE DECODER, AND SOFT DECISION VALUE CALCULATING METHOD 有权
标题翻译：软输出解码器，迭代解码器和软决策值计算方法
公开(公告)号：US20100169745A1
公开(公告)日：2010-07-01
申请号：US12377139
申请日：2007-08-21
申请人： Hiroyuki MOTOZUKA
发明人： Hiroyuki MOTOZUKA
IPC分类号： H03M13/45 , G06F11/10
CPC分类号： H03M13/2957 , H03M13/3905 , H03M13/3922 , H03M13/3927 , H03M13/3972 , H03M13/6502
摘要： A soft output decoder capable of performing decoding with a small computational complexity necessary for likelihood calculation thereby to reduce the scale of the operation circuit and to shorten the processing delay time. The soft output decoder (100) comprises a &ggr;α calculating section (101), timing adjusters (102, 103), a &ggr;β calculation section (104), and a &Lgr; calculating unit (110). The &Lgr; calculating unit (110) is composed of a hard decision decoding section (111), a loss likelihood calculating section (112), a win likelihood storage section (113), and a subtractor (114). The likelihoods determined by a Max-log-MAP decoder are separated into win likelihoods and loss likelihoods, and only the loss likelihoods are calculated. A hard decision decoding section (111) for sequentially specifying the states through which the maximum likelihood path passes is used for a method for distinguishing the win and loss likelihoods.
摘要翻译：一种软输出解码器，其能够以可能性计算所需的小计算复杂度进行解码，从而减小运算电路的比例并缩短处理延迟时间。软输出解码器（100）包括一个计算部分（101），定时调整器（102,103），一个＆ggr;＆bgr; 计算部（104）和＆Lgr; 计算单元（110）。 The＆Lgr 计算单元（110）由硬判决解码部（111），损失似然度计算部（112），胜利可能性存储部（113）和减法器（114）构成。由Max-log-MAP解码器确定的可能性被分为胜利可能性和损失似然性，并且仅计算损失似然性。用于顺序地指定最大似然路径通过的状态的硬判决解码部分（111）被用于区分胜利和丢失可能性的方法。

4. 发明申请

US20070005346A1 Mobile terminal device 审中-公开
标题翻译：移动终端设备
公开(公告)号：US20070005346A1
公开(公告)日：2007-01-04
申请号：US10578925
申请日：2004-10-25
申请人： Shinji Ueda , Hiroyuki Motozuka , Tomohiro Imai
发明人： Shinji Ueda , Hiroyuki Motozuka , Tomohiro Imai
IPC分类号： G10L11/00 , G09G5/00
CPC分类号： G06F3/0237 , H04M2250/70
摘要： A mobile terminal apparatus that considers intervals between key input operations when characters are input, and, when there is an interval grater than a certain period of time between operations, or when a shift is made to different character input, reads aloud the voice corresponding to the stored input character and reads aloud only the character the user needs to check. In this apparatus, when other characters are continuously input by the same key input within a predetermined time, character selection fixing section 201 updates the stored content in present candidate storage section 202, outputs the updated candidate character to display control section 204 as a displaying character and displays the updated candidate character on liquid crystal display section 103. At this time, the voice corresponding to the displaying candidate character is not reproduced. When the predetermined time passes without key input, character selection fixing section 201 reads aloud the present candidate character stored in present candidate storage section 202, outputs the present candidate character to reading determination section 206 as a fixed character, and voice reproduction section 105 reproduces the voice corresponding to the fixed character.
摘要翻译：一种移动终端装置，其考虑输入字符时的键输入操作之间的间隔，并且当存在比操作之间的一定时间段更长的间隔时，或者当对不同的字符输入进行移位时，朗读对应于存储的输入字符，并且只朗读用户需要检查的字符。在该装置中，当在预定时间内通过相同的键输入连续地输入其他字符时，字符选择确定部分201更新当前候选存储部分202中存储的内容，将更新的候选字符输出到显示控制部分204作为显示字符并且在液晶显示部103上显示更新的候选字符。此时，不再现与显示候补字符对应的声音。当没有键输入的预定时间过去时，字符选择确定部分201朗读当前候选存储部分202中存储的当前候选字符，将当前候选字符作为固定字符输出到读取确定部分206，并且语音再现部分105再现对应固定字符的声音。

5. 发明授权

US08261163B2 Soft output decoder, iterative decoder, and soft decision value calculating method 有权
标题翻译：软输出解码器，迭代解码器和软判决值计算方法
公开(公告)号：US08261163B2
公开(公告)日：2012-09-04
申请号：US12377139
申请日：2007-08-21
申请人： Hiroyuki Motozuka
发明人： Hiroyuki Motozuka
IPC分类号： H03M13/00
CPC分类号： H03M13/2957 , H03M13/3905 , H03M13/3922 , H03M13/3927 , H03M13/3972 , H03M13/6502
摘要： A soft output decoder that receives code words corresponding to information words is provided. The soft output decoder calculates soft decision decoding results of the information words from likelihood values corresponding to candidate values adopted by the information words. The soft output decoder includes a hard decision decoder that decides one of the candidate values as an estimated value. The soft output decoder further includes a likelihood calculator that bans calculation of a likelihood value corresponding to the estimated value and that calculates other likelihood values corresponding to other candidate values in the likelihood values.
摘要翻译：提供接收与信息字对应的代码字的软输出解码器。软输出解码器从与信息字所采用的候选值相对应的似然值计算信息字的软判决解码结果。软输出解码器包括将候选值中的一个确定为估计值的硬判决解码器。软输出解码器还包括：似然计算器，其禁止与估计值相对应的似然值的计算，并计算与似然值中的其他候选值相对应的其他似然值。

6. 发明申请

US20100205518A1 RUNNING CYCLIC REDUNDANCY CHECK OVER CODING SEGMENTS 审中-公开
标题翻译：运行循环冗余检查代码段
公开(公告)号：US20100205518A1
公开(公告)日：2010-08-12
申请号：US12673569
申请日：2008-08-18
申请人： Alexander Golitschek Edler von Elbwart , Hiroyuki Motozuka
发明人： Alexander Golitschek Edler von Elbwart , Hiroyuki Motozuka
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H03M13/09 , H04L1/0041 , H04L1/0061 , H04L1/0083 , H04L1/1812
摘要： In order to allow early stopping of codeblock decoding iterations, a cyclic redundancy check (CRC) is attached to each codeblock segment that pertains to the same transport block carrying information bits. The CRC for segment k is calculated for all bits within segments 1 to k. This allows also identifying cases of wrongly assumed CRC check results for segments 1 to k when the CRC attached to segment k+1 is evaluated.
摘要翻译：为了允许早期停止码块解码迭代，循环冗余校验（CRC）被附加到与携带信息比特的相同传输块相关的每个码块段。针对段1至k中的所有位计算段k的CRC。这允许当评估附加到段k + 1的CRC时，识别段1至k的错误假定的CRC校验结果的情况。

7. 发明申请

US20100198892A1 PARALLEL RESIDUE ARITHMETIC OPERATION UNIT AND PARALLEL RESIDUE ARITHMETIC OPERATING METHOD 有权
标题翻译：并行算术运算单元和平行残差算术运算方法
公开(公告)号：US20100198892A1
公开(公告)日：2010-08-05
申请号：US12377772
申请日：2007-08-21
申请人： Hiroyuki Motozuka
发明人： Hiroyuki Motozuka
IPC分类号： G06F17/11 , G06F7/38
CPC分类号： H03M13/091
摘要： A parallel residue arithmetic operation unit is provided to make it possible to reduce processing delay, and to make an additional multiplier or a residue arithmetic circuit unnecessary, so that a circuit can become small in size. In the parallel residue arithmetic operation unit, a parallel CRC calculation circuit (100) is comprised of input terminals (101)-(104) to which input data are divided into a plurality of sub-blocks and the sub-blocks are input in parallel, an initial value generating unit (110) for generating a part CRC corresponding to the forefront of each sub-block as an initial value, a part CRC generating unit (111)-(114) for receiving the part CRC corresponding to the forefront of each sub-block as the initial value and sequentially generating a residue part CRC in accordance with a recurrent equation, AND units (121)-(124) for calculating logical multiplications of part CRC values, and a cumulative adding unit (130) for cumulatively adding values output from the AND units (121)-(124).
摘要翻译：提供并行残余算术运算单元，以减少处理延迟，并且不需要额外的乘法器或残余运算电路，使得电路的尺寸变小。在并行残差运算单元中，并行CRC计算电路（100）由输入端子（101）〜（104）构成，输入数据被分割为多个子块，并且子块被并行输入，用于产生与每个子块的最前面相对应的部分CRC作为初始值的初始值生成单元（110），用于接收对应于最前面的部分CRC的部分CRC生成单元（111） - （114）每个子块作为初始值，并且根据复现方程依次产生残余部分CRC，用于计算部分CRC值的逻辑乘法的AND单元（121） - （124）和累积加法单元（130）添加从AND单元（121）输出的值（124）。

8. 发明申请

US20070067379A1 Data processing apparatus 审中-公开
标题翻译：数据处理装置
公开(公告)号：US20070067379A1
公开(公告)日：2007-03-22
申请号：US10575861
申请日：2004-10-06
申请人： Hiroyuki Motozuka , Ryutaro Yamanaka
发明人： Hiroyuki Motozuka , Ryutaro Yamanaka
IPC分类号： G06F7/38
CPC分类号： G06F15/8023 , G06F15/7867
摘要： A reconfigurable data processing apparatus. In this apparatus, many cells A 100 for performing ALU processing and cells B 150 for performing bit processing are arranged, each cell includes n-bit input/output ports and the cells are connected through a network with n-bit buses. Furthermore, when the number of output bits is smaller than n, cell B 150 fixes bits of orders irrelevant to outputs to “0” or “1.” When the bussed ALU processing part and bit processing part are combined to perform data processing, this makes it possible to execute ALU processing and bit processing efficiently and realize high-speed, parallel processing.
摘要翻译：一种可重构数据处理装置。在该装置中，配置用于执行ALU处理的许多单元A 100和用于执行位处理的单元B 150，每个单元包括n位输入/输出端口，并且单元通过具有n位总线的网络连接。此外，当输出位数小于n时，单元B 150将与输出无关的位的位固定为“0”或“1”。当总线的ALU处理部分和位处理部分被组合以执行数据处理时，这使得可以有效地执行ALU处理和位处理并实现高速并行处理。

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