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    • 2. 发明授权
    • Circuit array substrate for display device
    • 用于显示装置的电路阵列基板
    • US07042149B2
    • 2006-05-09
    • US10456584
    • 2003-06-09
    • Hirotaka Shigeno
    • Hirotaka Shigeno
    • H01J1/62
    • G02F1/13458G02F1/13452H05K3/361H05K2201/09472H05K2201/09909
    • A circuit array substrate 10 includes pixel and connecting edge sections 80 and 90. Connecting edge section 90 is provided with edge portions 5a and shoulder portions 55 of transparent thin resin film 5 over which terminal pins 101 of tape carrier packages (TCP) 100 are disposed. Terminal pins 101 are connected to connecting pads 14 at their contact portions 103. Shoulder portions 55 prevent a coated photoresist film from being excessive in depth and residues of the photoresist film from being left in the foot of edge face 5a in the step of forming metal reflective pixel electrodes. Thus, no residue of the metal film exists after its etching treatment in that step so that no electrical short circuits are caused between connecting pads 14 and adjacent terminal pins 101.
    • 电路阵列基板10包括像素和连接边缘部分80和90。 连接边缘部分90设置有透明薄树脂膜5的边缘部分5a和肩部55,在该部分上设有带状载体封装(TCP)100的端子引脚101。 端子销101在其接触部分103处连接到连接焊盘14。 在形成金属反射像素电极的步骤中,肩部55防止涂覆的光致抗蚀剂膜的深度过大,光刻胶膜的残留物残留在边缘面5a的脚中。 因此,在该步骤中的蚀刻处理之后,不存在金属膜残留物,使得在连接焊盘14和相邻的端子引脚101之间不产生电气短路。
    • 4. 发明授权
    • Array substrate used for a display device and a method of making the same
    • 用于显示装置的阵列基板及其制造方法
    • US07115913B2
    • 2006-10-03
    • US10395100
    • 2003-03-25
    • Hirotaka Shigeno
    • Hirotaka Shigeno
    • H01L21/00H01L29/205
    • H01L27/12G02F1/133555H01L27/1244H01L27/1248
    • A TFT array substrate used for a display device and a method of making the same are disclosed. A optically transparent thick resin insulation film 5 is formed on a base substrate and an upper contact hole 51 is perforated through the optically transparent thick resin insulation film 5. A lower contact hole 41 perforated through a gate insulation film 15 and patterning of an ITO film to make a transparent pixel electrode are then collectively carried out under a photoresist pattern 8. Where the photoresist pattern 8 is provided after making the ITO film, an aperture 81 is perforated closer to the center of the upper contact hole 51 at an end portion of a connecting line 14a for a pad and is smaller in diameter by a side etching size plus a margin than the upper contact hole. Subsequently, following three-etching steps are carried out: (1) patterning of the ITO film along the photoresist pattern 8, (2) the lower contact hole 41 is made by using buffered hydrofluoric acid solution, and (3) an “eaves” portion 6a of the ITO films is removed.
    • 公开了用于显示装置的TFT阵列基板及其制造方法。 光学透明的厚树脂绝缘膜5形成在基底基板上,并且上部接触孔51穿过光学透明的厚树脂绝缘膜5。 然后在光致抗蚀剂图案8下共同地进行穿过栅极绝缘膜15的下接触孔41和ITO膜的图案化以形成透明像素电极。 在制造ITO膜之后设置光致抗蚀剂图案8的情况下,在衬垫的连接线14a的端部处,孔81穿过更接近上接触孔51的中心,并且通过侧蚀刻具有较小的直径 尺寸加上边界比上接触孔。 随后,进行三蚀刻步骤:(1)沿着光致抗蚀剂图案8图案化ITO膜,(2)通过使用缓冲氢氟酸溶液制造下接触孔41,(3)“檐” 除去ITO膜的部分6a。
    • 5. 发明授权
    • Circuit array substrate for display device and method of manufacturing the same
    • 用于显示装置的电路阵列基板及其制造方法
    • US07021983B2
    • 2006-04-04
    • US11226233
    • 2005-09-15
    • Hirotaka Shigeno
    • Hirotaka Shigeno
    • H01J9/00
    • G02F1/13458G02F1/13452H05K3/361H05K2201/09472H05K2201/09909
    • A circuit array substrate 10 includes pixel and connecting edge sections 80 and 90. Connecting edge section 90 is provided with edge portions 5a and shoulder portions 55 of transparent thin resin film 5 over which terminal pins 101 of tape carrier packages (TCP) 100 are disposed. Terminal pins 101 are connected to connecting pads 14 at their contact portions 103. Shoulder portions 55 prevent a coated photoresist film from being excessive in depth and residues of the photoresist film from being left in the foot of edge face 5a in the step of forming metal reflective pixel electrodes. Thus, no residue of the metal film exists after its etching treatment in that step so that no electrical short circuits are caused between connecting pads 14 and adjacent terminal pins 101.
    • 电路阵列基板10包括像素和连接边缘部分80和90。 连接边缘部分90设置有透明薄树脂膜5的边缘部分5a和肩部55,在该部分上设有带状载体封装(TCP)100的端子引脚101。 端子销101在其接触部分103处连接到连接焊盘14。 在形成金属反射像素电极的步骤中,肩部55防止涂覆的光致抗蚀剂膜的深度过大,光刻胶膜的残留物残留在边缘面5a的脚中。 因此,在该步骤中的蚀刻处理之后,不存在金属膜残留物,使得在连接焊盘14和相邻的端子引脚101之间不产生电气短路。