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1. 发明授权

US08060853B2 Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method and semiconductor device 有权
标题翻译：半导体集成电路设计装置，半导体集成电路设计方法和半导体器件
公开(公告)号：US08060853B2
公开(公告)日：2011-11-15
申请号：US12108699
申请日：2008-04-24
申请人： Hiroshige Orita
发明人： Hiroshige Orita
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A semiconductor device includes a plurality of logical elements and a plurality of wiring lines. The plurality of wiring lines have a wiring line which connects the logical elements to each other, and a wiring line which is disconnected on one end from one of the logical elements and connected on the other end to another one of the logical elements.
摘要翻译：半导体器件包括多个逻辑元件和多个布线。多个布线具有将逻辑元件彼此连接的布线，以及从一个逻辑元件的一端与一个逻辑元件断开并在另一端连接到另一个逻辑元件的布线。

2. 发明申请

US20110191734A1 DESIGNING APPARATUS, DESIGNING METHOD, AND COMPUTER READABLE MEDIUM 审中-公开
标题翻译：设计设计，设计方法和计算机可读介质
公开(公告)号：US20110191734A1
公开(公告)日：2011-08-04
申请号：US12887044
申请日：2010-09-21
申请人： Jiro HAYAKAWA , Naoyuki KAWABE , Hiroshige ORITA , Takashi BAN
发明人： Jiro HAYAKAWA , Naoyuki KAWABE , Hiroshige ORITA , Takashi BAN
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： In general, according to one embodiment, a designing apparatus includes a clock tree generator, a logic modifier, a layout modifier, and an outputting module. The clock tree generator is configured to generate a clock tree. The logic modifier is configured to logically insert a delay element in such a manner that a hold violation is modified without considering a setup timing with respect to circuit data corresponding to the clock tree generated by the clock tree generator. The layout modifier is configured to modify a layout of a semiconductor integrated circuit based on a processing result of the logic modifier. The outputting module is configured to output the layout of the semiconductor integrated circuit. The layout is modified by the layout modifier.
摘要翻译：通常，根据一个实施例，设计装置包括时钟树生成器，逻辑修改器，布局修改器和输出模块。时钟树生成器被配置为生成时钟树。逻辑修改器被配置为逻辑地插入延迟元件，使得在不考虑与由时钟树生成器生成的时钟树相对应的电路数据的设置定时的情况下修改保持违例。布局修改器被配置为基于逻辑修改器的处理结果来修改半导体集成电路的布局。输出模块被配置为输出半导体集成电路的布局。布局由布局修改器修改。

3. 发明申请

US20080270957A1 SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING METHOD AND SEMICONDUCTOR DEVICE 有权
标题翻译：半导体集成电路设计装置，半导体集成电路设计方法和半导体器件
公开(公告)号：US20080270957A1
公开(公告)日：2008-10-30
申请号：US12108699
申请日：2008-04-24
申请人： Hiroshige Orita
发明人： Hiroshige Orita
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A semiconductor device includes a plurality of logical elements and a plurality of wiring lines. The plurality of wiring lines have a wiring line which connects the logical elements to each other, and a wiring line which is disconnected on one end from one of the logical elements and connected on the other end to another one of the logical elements.
摘要翻译：半导体器件包括多个逻辑元件和多个布线。多个布线具有将逻辑元件彼此连接的布线，以及从一个逻辑元件的一端与一个逻辑元件断开并在另一端连接到另一个逻辑元件的布线。

4. 发明申请

US20050160391A1 Semiconductor integrated circuit having multi-level interconnection, CAD method and CAD tool for designing the semiconductor integrated circuit 失效
标题翻译：具有多层互连的半导体集成电路，用于设计半导体集成电路的CAD方法和CAD工具
公开(公告)号：US20050160391A1
公开(公告)日：2005-07-21
申请号：US11019922
申请日：2004-12-20
申请人： Hiroshige Orita
发明人： Hiroshige Orita
IPC分类号： G06F17/50 , H01L21/3205 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/04
CPC分类号： G06F17/5022 , G06F17/5077 , G06F2217/78 , H01L2924/0002 , H01L2924/00
摘要： A computer-aided design method of an integrated circuit includes: calculating current dissipation consumed by logic elements, in a ladder network embracing a plurality of current paths connected between subject first- and second-potential-level power supply wiring; analyzing a tolerable electro-migration current of the subject first-potential-level power supply wiring; analyzing an interval voltage drop between a control point and a specific position on the subject first-potential-level power supply wiring; and comparing a summation of through-currents flowing the logic elements from the control point to the specific point, with the tolerable electro-migration current, and comparing the interval voltage drop with a tolerable voltage drop to determine an optimum location of a via configured to supply power from the subject first-potential-level power supply wiring to the logic elements.
摘要翻译：集成电路的计算机辅助设计方法包括：在包含连接在对象第一和第二电位电源布线之间的多个电流路径的梯形网络中计算由逻辑元件消耗的电流消耗; 分析对象第一电位电源布线的可容许的电迁移电流; 分析所述对象第一电位电源布线上的控制点与特定位置之间的间隔电压降; 以及将来自控制点的逻辑元件的流过的电流与允许的电迁移电流进行比较，并将间隔电压降与可容忍的电压降进行比较，以确定通孔的最佳位置被配置为从主体第一电位电源布线向逻辑元件供电。

5. 发明申请

US20090020850A1 SEMICONDUCTOR DESIGN APPARATUS, SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DESIGN METHOD 审中-公开
标题翻译：半导体设计装置，半导体电路和半导体设计方法
公开(公告)号：US20090020850A1
公开(公告)日：2009-01-22
申请号：US12174921
申请日：2008-07-17
申请人： Hiroshige Orita , Kazunari Kimura , Toshiaki Mori
发明人： Hiroshige Orita , Kazunari Kimura , Toshiaki Mori
IPC分类号： H01L23/64 , G06F17/50
CPC分类号： H01L23/5223 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： According to an aspect of the present invention, there is provided a semiconductor design apparatus including: a determination section that determines a connection position of a capacitor to suppress a noise on a layout data in which a layout of circuit cells are completed; a calculation section that calculates a capacitance value required to suppress the noise; a generation section that generates the capacitor satisfying the capacitance value; and a wiring section that wires the capacitor to a power wiring and a ground wiring at the connection position.
摘要翻译：根据本发明的一个方面，提供了一种半导体设计装置，包括：确定部，确定电容器的连接位置，以抑制电路单元布局完成的布局数据上的噪声; 计算部，其计算抑制噪声所需的电容值; 产生满足电容值的电容器的发生部分; 以及将电容器连接到连接位置处的电力布线和接地布线的布线部。

6. 发明授权

US07272810B2 Semiconductor integrated circuit having multi-level interconnection, CAD method and CAD tool for designing the semiconductor integrated circuit 失效
标题翻译：具有多层互连的半导体集成电路，用于设计半导体集成电路的CAD方法和CAD工具
公开(公告)号：US07272810B2
公开(公告)日：2007-09-18
申请号：US11019922
申请日：2004-12-20
申请人： Hiroshige Orita
发明人： Hiroshige Orita
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5077 , G06F2217/78 , H01L2924/0002 , H01L2924/00
摘要： A computer-aided design method of an integrated circuit includes: calculating current dissipation consumed by logic elements, in a ladder network embracing a plurality of current paths connected between subject first- and second-potential-level power supply wiring; analyzing a tolerable electro-migration current of the subject first-potential-level power supply wiring; analyzing an interval voltage drop between a control point and a specific position on the subject first-potential-level power supply wiring; and comparing a summation of through-currents flowing the logic elements from the control point to the specific point, with the tolerable electro-migration current, and comparing the interval voltage drop with a tolerable voltage drop to determine an optimum location of a via configured to supply power from the subject first-potential-level power supply wiring to the logic elements.
摘要翻译：集成电路的计算机辅助设计方法包括：在包含连接在对象第一和第二电位电源布线之间的多个电流路径的梯形网络中计算由逻辑元件消耗的电流消耗; 分析对象第一电位电源布线的可容许的电迁移电流; 分析所述对象第一电位电源布线上的控制点与特定位置之间的间隔电压降; 以及将来自控制点的逻辑元件的流过的电流与允许的电迁移电流进行比较，并将间隔电压降与可容忍的电压降进行比较，以确定通孔的最佳位置被配置为从主体第一电位电源布线向逻辑元件供电。

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