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    • 2. 发明授权
    • Method and apparatus for inserting terminal-carrying wire ends into a
connector housing
    • 将端子承载线末端插入连接器壳体中的方法和装置
    • US5127159A
    • 1992-07-07
    • US684457
    • 1991-04-12
    • Shigeji KudoSanae SuzukiHideaki MoritaHiroo Suzuki
    • Shigeji KudoSanae SuzukiHideaki MoritaHiroo Suzuki
    • H01R43/20H01R43/28
    • H01R43/28H01R43/20Y10T29/49181Y10T29/49185Y10T29/514Y10T29/53235Y10T29/53239
    • Described herein is a method and an apparatus which permit terminal-carrying ends of wire units to be automatically inserted into a connector housing in a reliable manner almost irrespective of the type and size of the terminal elements to be inserted. This is attained by providing a transfer plate which is movable to a position confronting a selected one of a plurality of connector housings set on an assembling table. An assembling head is mounted on the transfer plate movably in vertical directions and also in directions toward and away from the transfer plate. A wire-embracing terminal portion and a wire portion of the wire unit are gripped by means of openable and closable paired terminal gripping pawls and wire gripping pawls which are vertically movably supported on the assembling head. The posture of the terminal element is adjusted by lowering a terminal presser plate which is vertically movably provided between the paired terminal gripping pawls. The assembling head is moved toward the connector housing to insert the terminal element into the connector housing. The terminal gripping pawls are opened and lifted up as soon as an electric contact portion of the terminal element is inserted into a terminal compartment of the connector housing.
    • 这里描述了允许线单元的端子承载端以可靠的方式自动插入连接器壳体中的方法和装置,几乎不考虑要插入的端子元件的类型和尺寸。 这通过提供可移动到面对设置在组装台上的多个连接器壳体中的选定的一个的位置的转移板来实现。 组装头在垂直方向以及朝向和远离转印板的方向上可移动地安装在转印板上。 通过可开启和关闭的成对的端子夹持爪和线夹紧爪来夹持线组件的线束端子部分和线部分,其可垂直运动地支撑在组装头上。 终端元件的姿势通过下降可沿垂直方向设置在成对的端子夹持爪之间的端子压板来调节。 组装头朝向连接器壳体移动,以将端子元件插入连接器壳体中。 一旦端子元件的电接触部分插入连接器壳体的端子室中,端子夹爪被打开并提起。
    • 8. 发明授权
    • Logic signal selection circuit
    • 逻辑信号选择电路
    • US6025747A
    • 2000-02-15
    • US765539
    • 1997-09-02
    • Toshiyuki OkayasuHiroo Suzuki
    • Toshiyuki OkayasuHiroo Suzuki
    • H03K17/00H03K17/62
    • H03K17/005
    • It is to achieve a logic signal selection circuit having high timing resolution and high speed. The logic signal selection circuit includes a current input type sense amplifier 320 which is provided with a threshold value which is an output of an equivalent center current generator 310 and positive logic input signals through transfer gates, a current input type sense amplifier 321 which is provided with a threshold value which is an output of an equivalent center current generator 311 and negative logic input signals through transfer gates, a differential amplifier 340 which receives and amplifies an output of the current input type sense amplifier 320 whose delay times are fine adjusted by a delay time adjuster 330, a differential amplifier 341 which receives and amplifies an output of the current input type sense amplifier 321 whose delay times are fine adjusted by a delay time adjuster 331, and a logic circuit 350 which receives both outputs of the differential amplifiers 340 and 341, and generates a logical sum of the both outputs. Because there is no voltage change in the input of the current input type sense amplifier, current flows will not occur to the capacitance C of the transfer gates which are in the OFF state and connected at the input of the current input type sense amplifier. Thus, it is able to output the selected input signal with high timing resolution and with high speed.
    • PCT No.PCT / JP96 / 01650 Sec。 371日期:1997年9月2日 102(e)1997年9月2日PCT PCT 1996年6月17日PCT公布。 公开号WO97 / 00557 日期1997年1月3日是实现具有高定时分辨率和高速度的逻辑信号选择电路。 逻辑信号选择电路包括电流输入型读出放大器320,该电流输入型读出放大器320具有作为等效中心电流发生器310的输出的阈值和通过传输门的正逻辑输入信号,提供的电流输入型读出放大器321 具有作为等效中心电流发生器311的输出的阈值和通过传输门的负逻辑输入信号的差分放大器340,其差分放大器340接收并放大当前输入型读出放大器320的延迟时间由 延迟时间调整器330,差分放大器341,其接收并放大其延迟时间被延迟时间调整器331微调的当前输入型读出放大器321的输出;以及逻辑电路350,其接收差分放大器340的两个输出 和341,并且产生两个输出的逻辑和。 由于在当前输入型读出放大器的输入端没有电压变化,所以不会对处于截止状态并连接在当前输入型读出放大器的输入端的传输门的电容C产生电流。 因此,能够以高定时分辨率和高速度输出所选择的输入信号。