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1. 发明申请

US20120027203A1 INTERFACE CIRCUIT 审中-公开
标题翻译：接口电路
公开(公告)号：US20120027203A1
公开(公告)日：2012-02-02
申请号：US13188726
申请日：2011-07-22
申请人： Hirofumi Inada
发明人： Hirofumi Inada
IPC分类号： H04L9/18
CPC分类号： H04L9/0662 , G09G5/006 , G09G2358/00 , G09G2370/12 , H04L7/04 , H04L9/12 , H04L2209/122
摘要： A decoder extracts a synchronization signal from a data stream received via an active port. Synchronization signal generators are arranged for respective ports, and each is configured such that, when it receives a synchronization signal for the corresponding port from the decoder, it cyclically generates a replica of the synchronization signal for the port. When the synchronization signal received from the decoder or the synchronization signal generator is asserted, a first calculation module calculates authentication data. When the synchronization signal for the active port is asserted, a second calculation module generates a decipher code used to decipher the data stream input to the active port, using data obtained by the calculation processing of the first calculation module.
摘要翻译：解码器从经由活动端口接收的数据流中提取同步信号。同步信号发生器被布置用于相应的端口，并且每个端口被配置为使得当其从解码器接收到对应的端口的同步信号时，循环地生成端口的同步信号的副本。当从解码器或同步信号发生器接收的同步信号被断言时，第一计算模块计算认证数据。当有效端口的同步信号被断言时，第二计算模块使用通过第一计算模块的计算处理获得的数据来生成用于解密输入到活动端口的数据流的译码码。

2. 发明申请

US20090072870A1 DIGITAL SIGNAL PROCESSING CIRCUIT 审中-公开
标题翻译：数字信号处理电路
公开(公告)号：US20090072870A1
公开(公告)日：2009-03-19
申请号：US11959628
申请日：2007-12-19
申请人： Hirofumi Inada
发明人： Hirofumi Inada
IPC分类号： H03B19/10
CPC分类号： H03M5/22
摘要： A digital signal processing circuit performs a predetermined computation processing on input data sequentially input at a first frequency, and generates output data of a second frequency oversampled to n times (n is an integer greater than or equal to 2). A computation processing unit collectively computes m (m is 2≦m≦n) successive output data in output data at n sampling timings after oversampling. A data holding unit holds data at a predetermined sampling timing in the data generated in the computation processing unit. An output data holding unit holds data at m sampling timings to be output. An output data generating unit sequentially outputs m output data obtained by the computation processing unit according to a second frequency.
摘要翻译：数字信号处理电路对以第一频率顺序输入的输入数据执行预定的计算处理，并且产生第二频率被过采样到n次的输出数据（n是大于或等于2的整数）。计算处理单元在过采样之后的n个采样定时处统计计算输出数据中的m（m = 2 <= m <= n）个连续输出数据。数据保持单元在计算处理单元中生成的数据中以预定的采样定时保持数据。输出数据保持单元以m个采样定时保存要输出的数据。输出数据生成单元根据第二频率顺序地输出由计算处理单元获得的m个输出数据。

3. 发明授权

US5341324A Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5341324A
公开(公告)日：1994-08-23
申请号：US953699
申请日：1992-09-30
申请人： Toshiyuki Matsumoto , Hirofumi Inada , Hiroshi Nittaya , Masahiro Kato
发明人： Toshiyuki Matsumoto , Hirofumi Inada , Hiroshi Nittaya , Masahiro Kato
IPC分类号： G02F1/1345 , G02F1/136 , G02F1/1368 , H01L21/822 , H01L21/8234 , H01L21/8244 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/11 , G11C11/24
CPC分类号： H01L27/1104 , H01L27/11
摘要： A gate electrode of a P-channel MOS transistor and a gate electrode of an N-channel MOS transistor which constitute a logic section, a gate electrode of an N-channel MOS transistor and a capacitor electrode which constitute a memory cell section are formed by patterning a first layer of polysilicon, so that the semiconductor device can be manufactured in a considerably simplified process as an SRAM, while taking advantage of the large capacity of a DRAM thereby to improve the yield.
摘要翻译：构成逻辑部分的P沟道MOS晶体管的栅电极和N沟道MOS晶体管的栅电极，构成存储单元部分的N沟道MOS晶体管的栅极和电容器电极形成为：图案化第一层多晶硅，使得半导体器件可以以相当简化的工艺制造为SRAM，同时利用DRAM的大容量，从而提高产量。

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