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    • 1. 发明授权
    • Path determination method and computer-readable storage medium determining a path within a path determination region with an improved utilization efficiency
    • 路径确定方法和计算机可读存储介质,其确定路径确定区域内的路径,并提高利用效率
    • US06775710B1
    • 2004-08-10
    • US09678669
    • 2000-10-04
    • Hirofumi Hamamura
    • Hirofumi Hamamura
    • G06F15173
    • G06F17/5077
    • A path determination method includes the steps of (a) determining a path in a first region which has a utilization efficiency less than a predetermined value probability-wise, (b) determining a path in a second region which is different from the first region when the utilization efficiency of the first region exceeds a second predetermined value, where the second region has a utilization efficiency exceeding the first predetermined value probability-wise, (c) dividing an entire region which is to be subjected to a path determination into partial regions of predetermined sizes and using the partial regions as a minimum unit of path search, (d) assigning to each of the partial regions a state quantity which is described by a path accommodating capacity within each of the partial regions, and (e) searching a path between two points by controlling a search speed depending on a change in the state quantity between adjacent partial regions.
    • 路径确定方法包括以下步骤:(a)在概率上确定利用效率小于预定值的第一区域中的路径,(b)确定与第一区域不同的第二区域中的路径, 第一区域的利用效率超过第二预定值,其中第二区域具有超过第一预定值的利用效率,(c)将要进行路径确定的整个区域划分为部分区域 预定尺寸,并且使用部分区域作为路径搜索的最小单位,(d)向每个部分区域分配由每个部分区域内容纳容量的路径描述的状态量,以及(e)搜索路径 通过根据相邻部分区域之间的状态量的变化来控制搜索速度在两点之间。
    • 3. 发明授权
    • Logical simulation device
    • 逻辑仿真设备
    • US07516059B2
    • 2009-04-07
    • US11166156
    • 2005-06-27
    • Hiroaki KomatsuHirofumi Hamamura
    • Hiroaki KomatsuHirofumi Hamamura
    • G06F17/50
    • G06F17/5022
    • A logical simulation device executes simulation, based on cycle, using level sort and compile methods. In order to realize the high speed of the entire system in a practically usable scale, the system comprises a lot of processors, each capable of performing an evaluation process of executing simulation using a logical block corresponding to one or more gates as an evaluation unit, and a communication process with the other processors. A plurality of processors constitute a processor group, and a plurality of processor groups are connected to each other to form a tree-shaped hierarchy.
    • 逻辑仿真设备基于循环,使用级别排序和编译方法执行仿真。 为了以实际可用的规模实现整个系统的高速度,该系统包括许多处理器,每个处理器能够使用与一个或多个门相对应的逻辑块来执行仿真的评估处理作为评估单元, 以及与其他处理器的通信过程。 多个处理器构成处理器组,并且多个处理器组彼此连接以形成树形层级。
    • 4. 发明申请
    • Logical simulation device
    • 逻辑仿真设备
    • US20050240388A1
    • 2005-10-27
    • US11166156
    • 2005-06-27
    • Hiroaki KomatsuHirofumi Hamamura
    • Hiroaki KomatsuHirofumi Hamamura
    • G06F17/50
    • G06F17/5022
    • A logical simulation device executes simulation, based on cycle, using level sort and compile methods. In order to realize the high speed of the entire system in a practically usable scale, the system comprises a lot of processors, each capable of performing an evaluation process of executing simulation using a logical block corresponding to one or more gates as an evaluation unit, and a communication process with the other processors. A plurality of processors constitute a processor group, and a plurality of processor groups are connected to each other to form a tree-shaped hierarchy.
    • 逻辑仿真设备基于循环,使用级别排序和编译方法执行仿真。 为了以实际可用的规模实现整个系统的高速度,该系统包括许多处理器,每个处理器能够使用与一个或多个门相对应的逻辑块来执行仿真的评估处理作为评估单元, 以及与其他处理器的通信过程。 多个处理器构成处理器组,并且多个处理器组彼此连接以形成树形层级。