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1. 发明申请

US20120205612A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120205612A1
公开(公告)日：2012-08-16
申请号：US13454625
申请日：2012-04-24
申请人： Hideyuki TABATA , Eiji ITO , Hirofumi INOUE
发明人： Hideyuki TABATA , Eiji ITO , Hirofumi INOUE
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L27/2481 , G11C13/00 , G11C13/0009 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.
摘要翻译：非易失性半导体存储器件包括半导体衬底; 形成在所述半导体衬底上的单元阵列块，并且包括多个堆叠的单元阵列层，每个堆叠的单元阵列层具有多个第一线，与所述多条第一线交叉的多个第二线，以及在所述第一和第二线的两个交点处连接的存储单元线条以及在单元阵列层的堆叠方向上延伸的多个通孔，以将每个单元阵列层中的第一或第二线分别连接到半导体基板。通孔连续地形成在多个单元阵列层中，并且具有相同的下端位置和上端位置的多个通孔与不同的单元阵列层中的第一或第二线连接。

2. 发明申请

US20090134431A1 NONVOLATILE SEMICONDUCTOR STORAGE APPARATUS AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：非挥发性半导体存储装置及其制造方法
公开(公告)号：US20090134431A1
公开(公告)日：2009-05-28
申请号：US12275794
申请日：2008-11-21
申请人： Hideyuki TABATA , Hiroyuki NAGASHIMA , Hirofumi INOUE , Kohichi KUBO , Masanori KOMURA
发明人： Hideyuki TABATA , Hiroyuki NAGASHIMA , Hirofumi INOUE , Kohichi KUBO , Masanori KOMURA
IPC分类号： H01L29/66 , H01L29/00 , H01L21/20
CPC分类号： H01L45/1675 , G11C13/00 , G11C13/0009 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/147
摘要： A nonvolatile semiconductor storage apparatus includes: a plurality of first wirings; a plurality of second wirings which cross the plurality of first wirings; and a memory cell which is connected between both the wirings at an intersection of the first and second wirings, and includes a variable resistive element operative to store information according to a change in resistance and includes a variable resistive element, wherein the memory cell is formed so that a cross section area of the variable resistive element becomes smaller than a cross section area of the other portion.
摘要翻译：非易失性半导体存储装置包括：多个第一布线; 跨过多个第一配线的多个第二配线; 以及存储单元，其连接在所述第一和第二布线的交叉点处的所述布线之间，并且包括可变电阻元件，用于根据电阻变化存储信息，并且包括可变电阻元件，其中形成所述存储单元使得可变电阻元件的横截面面积变得小于另一部分的横截面面积。

3. 发明授权

US08711604B2 Non-volatile semiconductor memory and data processing method in non-volatile semiconductor memory 有权
标题翻译：非挥发性半导体存储器中的非易失性半导体存储器和数据处理方法
公开(公告)号：US08711604B2
公开(公告)日：2014-04-29
申请号：US13544412
申请日：2012-07-09
申请人： Shigeki Kobayashi , Hideyuki Tabata
发明人： Shigeki Kobayashi , Hideyuki Tabata
IPC分类号： G11C11/00 , G06F11/10 , G11C29/04
CPC分类号： G06F11/1012 , B82Y10/00 , G06F11/10 , G06F11/1008 , G11C7/00 , G11C13/0002 , G11C13/0014 , G11C13/004 , G11C13/0069 , G11C13/025 , G11C2029/0411 , G11C2213/35 , G11C2213/72
摘要： A non-volatile semiconductor memory according to an embodiment includes: a data storage unit including a memory cell array and a writing circuit; an encoder that directs the writing circuit to write write data to the memory cell array; a writing determining circuit that determines whether the writing of the write data to the memory cell array within a predetermined number of writing operations fails or succeeds, inverts the write data to generate new write data when the writing of the write data fails, and directs the writing circuit to write the new write data to the memory cell array; a switching circuit that inverts read data which is read from the memory cell to generate new read data when the writing determining circuit determines that the writing of the write data fails; and a decoder that decodes the read data into the information data.
摘要翻译：根据实施例的非易失性半导体存储器包括：包括存储单元阵列和写入电路的数据存储单元; 引导写入电路将写数据写入存储单元阵列的编码器; 写入确定电路，其确定在预定数量的写入操作中写入数据到存储器单元阵列的写入是否失败，当写入数据的写入失败时，反转写入数据以产生新的写入数据，并指示写入电路将新写入数据写入存储单元阵列; 切换电路，当写入确定电路确定写入数据的写入失败时，反转从存储器单元读取的读取数据以产生新的读取数据; 以及将读取的数据解码为信息数据的解码器。

4. 发明授权

US08648471B2 Nonvolatile semiconductor memory device including a via-hole with a narrowing cross-section and method of manufacturing the same 有权
标题翻译：包括具有窄截面的通孔的非易失性半导体存储器件及其制造方法
公开(公告)号：US08648471B2
公开(公告)日：2014-02-11
申请号：US13454625
申请日：2012-04-24
申请人： Hideyuki Tabata , Eiji Ito , Hirofumi Inoue
发明人： Hideyuki Tabata , Eiji Ito , Hirofumi Inoue
IPC分类号： H01L23/48 , H01L23/52 , H01L23/40
CPC分类号： H01L27/2481 , G11C13/00 , G11C13/0009 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.
摘要翻译：非易失性半导体存储器件包括半导体衬底; 形成在所述半导体衬底上的单元阵列块，并且包括多个堆叠的单元阵列层，每个堆叠的单元阵列层具有多个第一线，与所述多条第一线交叉的多个第二线，以及在所述第一和第二线的两个交点处连接的存储单元线条以及在单元阵列层的堆叠方向上延伸的多个通孔，以将每个单元阵列层中的第一或第二线分别连接到半导体基板。通孔连续地形成在多个单元阵列层中，并且具有相同的下端位置和上端位置的多个通孔与不同的单元阵列层中的第一或第二线连接。

5. 发明申请

US20130182488A1 NON-VOLATILE SEMICONDUCTOR MEMORY AND DATA PROCESSING METHOD IN NON-VOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器中的非易失性半导体存储器和数据处理方法
公开(公告)号：US20130182488A1
公开(公告)日：2013-07-18
申请号：US13544412
申请日：2012-07-09
申请人： Shigeki KOBAYASHI , Hideyuki Tabata
发明人： Shigeki KOBAYASHI , Hideyuki Tabata
IPC分类号： G11C13/00 , G11C7/00
CPC分类号： G06F11/1012 , B82Y10/00 , G06F11/10 , G06F11/1008 , G11C7/00 , G11C13/0002 , G11C13/0014 , G11C13/004 , G11C13/0069 , G11C13/025 , G11C2029/0411 , G11C2213/35 , G11C2213/72
摘要： A non-volatile semiconductor memory according to an embodiment includes: a data storage unit including a memory cell array and a writing circuit; an encoder that directs the writing circuit to write write data to the memory cell array; a writing determining circuit that determines whether the writing of the write data to the memory cell array within a predetermined number of writing operations fails or succeeds, inverts the write data to generate new write data when the writing of the write data fails, and directs the writing circuit to write the new write data to the memory cell array; a switching circuit that inverts read data which is read from the memory cell to generate new read data when the writing determining circuit determines that the writing of the write data fails; and a decoder that decodes the read data into the information data.
摘要翻译：根据实施例的非易失性半导体存储器包括：包括存储单元阵列和写入电路的数据存储单元; 引导写入电路将写数据写入存储单元阵列的编码器; 写入确定电路，其确定在预定数量的写入操作中写入数据到存储器单元阵列的写入是否失败，当写入数据的写入失败时，反转写入数据以产生新的写入数据，并指示写入电路将新写入数据写入存储单元阵列; 切换电路，当写入确定电路确定写入数据的写入失败时，反转从存储器单元读取的读取数据以产生新的读取数据; 以及将读取的数据解码为信息数据的解码器。

6. 发明授权

US08044456B2 Nonvolatile semiconductor memory device and producing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08044456B2
公开(公告)日：2011-10-25
申请号：US12540092
申请日：2009-08-12
申请人： Hiroyuki Nagashima , Hirofumi Inoue , Hideyuki Tabata , Masanori Komura , Eiji Ito
发明人： Hiroyuki Nagashima , Hirofumi Inoue , Hideyuki Tabata , Masanori Komura , Eiji Ito
IPC分类号： H01L29/792
CPC分类号： H01L27/1116 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/105 , H01L27/115 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.
摘要翻译：单元阵列包括其中形成存储器单元的存储单元区域和设置在存储单元区域周围的外围区域。在存储单元区域中，第一线与第一方向平行地延伸，并且第一线在与第一方向正交的第二方向上以第一间隔重复形成。在周边区域中，位于第（4n-3）（n是正整数）的第一线和从预定位置起的第二方向的第（4n-2）个位置中的每一个在一个上具有接触连接部分在第一行的第一个方向的端部。在周边区域中，位于距规定位置的第二方向（4n-1）和第4n位置的第一线的第一线在第一线的第一方向的另一端侧具有接触连接部。接触连接部形成为与层叠方向延伸的接触插塞接触。

7. 发明申请

US20100213550A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100213550A1
公开(公告)日：2010-08-26
申请号：US12556005
申请日：2009-09-09
申请人： Hiroshi Kanno , Kenichi Murooka , Jun Hirota , Hideyuki Tabata
发明人： Hiroshi Kanno , Kenichi Murooka , Jun Hirota , Hideyuki Tabata
IPC分类号： H01L27/10
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/1027
摘要： The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Sii-xGex (0
摘要翻译：存储单元位于第一布线和第二布线之间的相应交点处。每个存储单元具有串联连接的整流元件和可变电阻元件。整流元件包括p型第一半导体区域和n型第二半导体区域。第一半导体区域至少部分地由硅 - 锗混合物（Sii-xGex（0

8. 发明申请

US20100038616A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PRODUCING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100038616A1
公开(公告)日：2010-02-18
申请号：US12540092
申请日：2009-08-12
申请人： Hiroyuki NAGASHIMA , Hirofumi Inoue , Hideyuki Tabata , Masanori Komura , Eiji Ito
发明人： Hiroyuki NAGASHIMA , Hirofumi Inoue , Hideyuki Tabata , Masanori Komura , Eiji Ito
IPC分类号： H01L47/00
CPC分类号： H01L27/1116 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/105 , H01L27/115 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.
摘要翻译：单元阵列包括其中形成存储器单元的存储单元区域和设置在存储单元区域周围的外围区域。在存储单元区域中，第一线与第一方向平行地延伸，并且第一线在与第一方向正交的第二方向上以第一间隔重复形成。在外围区域中，位于第（4n-3）（n为正整数）的第一线和从预定位置起的第二方向的第（4n-2）个位置中的每一个在一个上具有接触连接部在第一行的第一个方向的端部。在周边区域中，位于距规定位置的第二方向（4n-1）和第4n位置的第一线的第一线在第一线的第一方向的另一端侧具有接触连接部。接触连接部形成为与层叠方向延伸的接触插塞接触。

9. 发明申请

US20090137112A1 METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICES 审中-公开
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US20090137112A1
公开(公告)日：2009-05-28
申请号：US12275741
申请日：2008-11-21
申请人： Hideyuki TABATA , Hirofumi Inoue , Hiroyuki Nagashima , Kohichi Kubo
发明人： Hideyuki TABATA , Hirofumi Inoue , Hiroyuki Nagashima , Kohichi Kubo
IPC分类号： H01L21/768
CPC分类号： H01L27/2418 , H01L27/2409 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： A method of manufacturing nonvolatile semiconductor memory devices comprises forming a first wiring material; and stacking memory cell materials on the first wiring material, which configure memory cells each including a variable resistor operative to nonvolatilely store information in accordance with variation in resistance. The method also comprises forming a plurality of first parallel trenches in the first wiring material and the stacked memory cell materials, the first trenches extending in a first direction, thereby forming first lines extending in the first direction and memory cell materials self-aligned with the first lines and separated by the first trenches. The method further comprises burying an interlayer insulator in the first trenches to form a block body and stacking a second wiring material on the block body. The method also comprises forming a plurality of second parallel trenches in the block body with the second wiring material stacked thereon, the second trenches extending in a second direction crossing the first direction and having a depth reaching the upper surface of the first wiring material, thereby forming second lines extending in the second direction and memory cells self-aligned with the second lines and separated by the first and second trenches.
摘要翻译：制造非易失性半导体存储器件的方法包括：形成第一布线材料; 以及在第一布线材料上堆叠存储单元材料，其构造每个包括可变电阻器的存储单元，其可操作以根据电阻的变化来非易失性地存储信息。该方法还包括在第一布线材料和堆叠的存储单元材料中形成多个第一平行沟槽，第一沟槽沿第一方向延伸，从而形成沿第一方向延伸的第一线和与第一方向自对准的存储单元材料第一条线和第一条沟分开。该方法还包括在第一沟槽中埋设层间绝缘体以形成块体并将第二布线材料堆叠在块体上。该方法还包括在堆叠在其上的第二布线材料的块体中形成多个第二平行沟槽，第二沟槽沿与第一方向交叉的第二方向延伸并且具有到达第一布线材料的上表面的深度，从而形成沿着第二方向延伸的第二线和与第二线自对准并由第一和第二沟槽隔开的存储器单元。

10. 发明授权

US08183602B2 Nonvolatile semiconductor memory device including via-holes continuously formed through plural cell array layers 有权
标题翻译：包括通过多个单元阵列层连续形成的通孔的非易失性半导体存储器件
公开(公告)号：US08183602B2
公开(公告)日：2012-05-22
申请号：US12275682
申请日：2008-11-21
申请人： Hideyuki Tabata , Eiji Ito , Hirofumi Inoue
发明人： Hideyuki Tabata , Eiji Ito , Hirofumi Inoue
IPC分类号： H01L23/52
CPC分类号： H01L27/2481 , G11C13/00 , G11C13/0009 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines indifferent cell array layers.
摘要翻译：非易失性半导体存储器件包括半导体衬底; 形成在所述半导体衬底上的单元阵列块，并且包括多个堆叠的单元阵列层，每个堆叠的单元阵列层具有多个第一线，与所述多条第一线交叉的多个第二线，以及在所述第一和第二线的两个交点处连接的存储单元线条以及在单元阵列层的堆叠方向上延伸的多个通孔，以将每个单元阵列层中的第一或第二线分别连接到半导体基板。通孔连续地形成在多个单元阵列层中，并且具有相同的下端位置和上端位置的多个通孔连接到第一或第二线不同的单元阵列层。

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