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1. 发明申请

US20080181231A1 DATA PROCESSING DEVICE, DATA PROCESSING METHOD AND DATA PROCESSING PROGRAM 审中-公开
标题翻译：数据处理设备，数据处理方法和数据处理程序
公开(公告)号：US20080181231A1
公开(公告)日：2008-07-31
申请号：US11969581
申请日：2008-01-04
申请人： Kazumasa SONODA , Satoru Mashima , Hideyuki Kudou , Akira Hashimoto , Takahiro Yamamoto
发明人： Kazumasa SONODA , Satoru Mashima , Hideyuki Kudou , Akira Hashimoto , Takahiro Yamamoto
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/263 , H04L47/30
摘要： A data processing device connected to another data processing device through an asynchronous network to receive/transmit data from/to the other data processing device. The data processing device monitors an accumulation amount of a reception buffer for receiving data transmitted from the other data processing device, controls a self reception data processing clock based upon the monitored accumulation amount, transmits to the other data processing device transmission clock control information controlling a transmission clock in the other data processing device based upon the monitored accumulation amount, and controlling a self transmission clock based upon the clock control information transmitted from the other data processing device.
摘要翻译：一种数据处理装置，其通过异步网络与另一数据处理装置连接，以从另一数据处理装置接收/发送数据。数据处理装置监视用于接收从其他数据处理装置发送的数据的接收缓冲器的累积量，根据监视到的累积量来控制自身接收数据处理时钟，向其他数据处理装置发送控制发送时钟控制信息基于所监视的累积量在另一数据处理装置中的传输时钟，以及基于从其他数据处理装置发送的时钟控制信息来控制自发送时钟。

2. 发明授权

US07027440B2 Router having a function to prevent a packet sequence inversion 失效
公开(公告)号：US07027440B2
公开(公告)日：2006-04-11
申请号：US10105475
申请日：2002-03-25
申请人： Hideyuki Kudou , Yushi Murata , Yasushi Kurokawa
发明人： Hideyuki Kudou , Yushi Murata , Yasushi Kurokawa
IPC分类号： H04L12/413 , H04J3/04
CPC分类号： H04L67/1002 , H04L45/60 , H04L47/2408 , H04L47/2441 , H04L47/32 , H04L47/34 , H04L47/50 , H04L49/253
摘要： A router includes a plurality of control units connected in parallel, each having an input connected to a receiving interface and an output connected to a transmitting interface, and performing timing control of outgoing packets to the transmitting interface based on header information of incoming packets, the incoming packets being stored in a memory and the stored packets being transmitted to the transmitting interface in order of transmission of the outgoing packets. A distributing unit distributes transmitting sequence information, related to the stored packets in the memory, to other control units. The distributing unit determines whether a packet sequence inversion in the control unit occurs, based on a result of comparison of the transmitting sequence information received and the transmitting sequence information held by the control unit, inhibiting the transmission of the stored packets to the transmitting interface when the packet sequence invention is detected.

3. 发明授权

US07496034B2 Packet processing device implementing scheduling and priority for improved efficiency 有权
标题翻译：分组处理设备实现调度和优先级，提高效率
公开(公告)号：US07496034B2
公开(公告)日：2009-02-24
申请号：US11077868
申请日：2005-03-11
申请人： Hideyo Fukunaga , Katsumi Imamura , Yasushi Kurokawa , Hideyuki Kudou , Yoko Watanabe
发明人： Hideyo Fukunaga , Katsumi Imamura , Yasushi Kurokawa , Hideyuki Kudou , Yoko Watanabe
IPC分类号： H04L12/56
CPC分类号： H04L47/6215 , H04L47/50
摘要： A packet transmission device improved in packet transmission efficiency. Each packet input processor generates a pointer and identifies a packet type with respect to a received packet, and generates identification data including the pointer and the packet type identification result. A memory access controller detects a header readout amount of the packet based on the packet type identification result, generates first readout data including the header readout amount and a readout pointer indicative of a storage location of the packet in a shared memory, and adaptively reads out header data of the packet from the shared memory in accordance with the first readout data. A protocol processor analyzes the destination of the read header data, and a packet updater updates the old destination address of the packet to a new one to generate a packet with the updated destination address, and outputs the generated packet.
摘要翻译：分组传输设备提高了分组传输效率。每个分组输入处理器产生指针并且相对于接收到的分组标识分组类型，并且生成包括指针和分组类型识别结果的标识数据。存储器访问控制器基于分组类型识别结果来检测分组的报头读出量，产生包括报头读出量的第一读出数据和表示分组在共享存储器中的存储位置的读出指针，并自适应地读出根据第一读出数据来自共享存储器的分组的报头数据。协议处理器分析读取标题数据的目的地，并且分组更新器将分组的旧目的地地址更新为新的分组，以生成具有更新的目的地地址的分组，并输出生成的分组。

4. 发明申请

US20060098648A1 Packet transmission device 有权
标题翻译：分组传输设备
公开(公告)号：US20060098648A1
公开(公告)日：2006-05-11
申请号：US11077868
申请日：2005-03-11
申请人： Hideyo Fukunaga , Katsumi Imamura , Yasushi Kurokawa , Hideyuki Kudou , Yoko Watanabe
发明人： Hideyo Fukunaga , Katsumi Imamura , Yasushi Kurokawa , Hideyuki Kudou , Yoko Watanabe
IPC分类号： H04J3/14 , H04J1/16 , H04L1/00 , H04L12/26 , H04L12/56 , H04L12/28
CPC分类号： H04L47/6215 , H04L47/50
摘要： A packet transmission device improved in packet transmission efficiency. Each packet input processor generates a pointer and identifies a packet type with respect to a received packet, and generates identification data including the pointer and the packet type identification result. A memory access controller detects a header readout amount of the packet based on the packet type identification result, generates first readout data including the header readout amount and a readout pointer indicative of a storage location of the packet in a shared memory, and adaptively reads out header data of the packet from the shared memory in accordance with the first readout data. A protocol processor analyzes the destination of the read header data, and a packet updater updates the old destination address of the packet to a new one to generate a packet with the updated destination address, and outputs the generated packet.
摘要翻译：分组传输设备提高了分组传输效率。每个分组输入处理器产生指针并且相对于接收到的分组标识分组类型，并且生成包括指针和分组类型识别结果的标识数据。存储器访问控制器基于分组类型识别结果来检测分组的报头读出量，产生包括报头读出量的第一读出数据和表示分组在共享存储器中的存储位置的读出指针，并自适应地读出根据第一读出数据来自共享存储器的分组的报头数据。协议处理器分析读取标题数据的目的地，并且分组更新器将分组的旧目的地地址更新为新的分组，以生成具有更新的目的地地址的分组，并输出生成的分组。

5. 发明申请

US20070002848A1 Packet relay apparatus and packet relay method 审中-公开
标题翻译：分组中继装置和分组中继方法
公开(公告)号：US20070002848A1
公开(公告)日：2007-01-04
申请号：US11233649
申请日：2005-09-23
申请人： Hideyuki Kudou , Takeshi Miyaura , Marika Kawano
发明人： Hideyuki Kudou , Takeshi Miyaura , Marika Kawano
IPC分类号： H04L12/50
CPC分类号： H04L47/10 , H04L47/2416 , H04L47/2441 , H04L47/283 , H04L49/205
摘要： An output-band control unit extracts delay information indicating a delay state of a packet from a packet received, and controls a setting of an output band of the packet based on the delay information. A packet-transmission control unit updates the delay information based on the output band of which the setting is controlled by the output-band control unit and an internal delay that occurs internally with respect to a packet output in the output band, and transmits the packet with the delay information updated.
摘要翻译：输出频带控制单元从接收到的分组中提取表示分组的延迟状态的延迟信息，并根据延迟信息来控制分组的输出频带的设定。分组传输控制单元基于由输出频带控制单元控制设置的输出频带和相对于输出频带中输出的分组内部发生的内部延迟来更新延迟信息，并且发送分组延迟信息更新。

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