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1. 发明授权

US07902572B2 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US07902572B2
公开(公告)日：2011-03-08
申请号：US12122805
申请日：2008-05-19
申请人： Ho Kyun Ahn , Jong Won Lim , Jae Kyoung Mun , Hong Gu Ji , Woo Jin Chang , Hea Cheon Kim
发明人： Ho Kyun Ahn , Jong Won Lim , Jae Kyoung Mun , Hong Gu Ji , Woo Jin Chang , Hea Cheon Kim
IPC分类号： H01L31/072
CPC分类号： H01L29/812 , H01L29/42316 , H01L29/66462 , H01L29/66856 , H01L29/778
摘要： A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.
摘要翻译：提供了具有头部比脚部宽的T形或/或G字形精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

2. 发明申请

US20080251858A1 FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20080251858A1
公开(公告)日：2008-10-16
申请号：US12122805
申请日：2008-05-19
申请人： Ho Kyun AHN , Jong Won LIM , Jae Kyoung MUN , Hong Gu JI , Woo Jin CHANG , Hea Cheon KIM
发明人： Ho Kyun AHN , Jong Won LIM , Jae Kyoung MUN , Hong Gu JI , Woo Jin CHANG , Hea Cheon KIM
IPC分类号： H01L29/49
CPC分类号： H01L29/812 , H01L29/42316 , H01L29/66462 , H01L29/66856 , H01L29/778
摘要： A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.
摘要翻译：提供具有头部比脚部宽的T形或γ形的精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

3. 发明授权

US07419862B2 Method of fabricating pseudomorphic high electron mobility transistor 有权
标题翻译：制造假型高电子迁移率晶体管的方法
公开(公告)号：US07419862B2
公开(公告)日：2008-09-02
申请号：US11446750
申请日：2006-06-05
申请人： Jong Won Lim , Ho Kyun Ahn , Hong Gu Ji , Woo Jin Chang , Jae Kyoung Mun , Hea Cheon Kim
发明人： Jong Won Lim , Ho Kyun Ahn , Hong Gu Ji , Woo Jin Chang , Jae Kyoung Mun , Hea Cheon Kim
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7784 , H01L29/1029 , H01L29/66462
摘要： Provided is a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT). The method includes the steps of: preparing a substrate including a channel layer and a capping layer that is the uppermost layer; forming a source and a drain on the capping layer; forming a first protective layer on the entire surface of the resultant structure and then patterning the first protective layer to expose a portion of the capping layer in a channel region; removing the exposed portion of the capping layer to form a first recess structure; forming a second protective layer on the entire surface of the resultant structure and then patterning the second protective layer to expose a portion of the substrate in the first recess structure so that a second recess structure is formed; forming a multilayered photoresist layer on the entire surface of the resultant structure and then patterning the multilayered photoresist layer to expose a portion of the substrate through the second recess structure and form a gate-shaped opening; and depositing a metal layer to fill the gate-shaped opening and then removing the multilayered photoresist layer to form a gate connected to the substrate through the second recess structure.
摘要翻译：提供了制造假象高电子迁移率晶体管（PHEMT）的方法。该方法包括以下步骤：制备包括沟道层和作为最上层的覆盖层的衬底; 在封盖层上形成源极和漏极; 在所得结构的整个表面上形成第一保护层，然后图案化第一保护层以暴露沟道区中的覆盖层的一部分; 去除所述覆盖层的暴露部分以形成第一凹陷结构; 在所得结构的整个表面上形成第二保护层，然后构图第二保护层，以暴露第一凹陷结构中的基底的一部分，从而形成第二凹陷结构; 在所得结构的整个表面上形成多层光致抗蚀剂层，然后构图多层光致抗蚀剂层，以通过第二凹陷结构暴露出基板的一部分并形成栅极形开口; 以及沉积金属层以填充所述栅极开口，然后移除所述多层光致抗蚀剂层，以形成通过所述第二凹陷结构连接到所述衬底的栅极。

4. 发明申请

US20070134862A1 Method of fabricating pseudomorphic high electron mobility transistor 有权
标题翻译：制造假型高电子迁移率晶体管的方法
公开(公告)号：US20070134862A1
公开(公告)日：2007-06-14
申请号：US11446750
申请日：2006-06-05
申请人： Jong Won Lim , Ho Kyun Ahn , Hong Gu Ji , Woo Jin Chang , Jae Kyoung Mun , Hea Cheon Kim
发明人： Jong Won Lim , Ho Kyun Ahn , Hong Gu Ji , Woo Jin Chang , Jae Kyoung Mun , Hea Cheon Kim
IPC分类号： H01L21/8234
CPC分类号： H01L29/7784 , H01L29/1029 , H01L29/66462
摘要： Provided is a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT). The method includes the steps of: preparing a substrate including a channel layer and a capping layer that is the uppermost layer; forming a source and a drain on the capping layer; forming a first protective layer on the entire surface of the resultant structure and then patterning the first protective layer to expose a portion of the capping layer in a channel region; removing the exposed portion of the capping layer to form a first recess structure; forming a second protective layer on the entire surface of the resultant structure and then patterning the second protective layer to expose a portion of the substrate in the first recess structure so that a second recess structure is formed; forming a multilayered photoresist layer on the entire surface of the resultant structure and then patterning the multilayered photoresist layer to expose a portion of the substrate through the second recess structure and form a gate-shaped opening; and depositing a metal layer to fill the gate-shaped opening and then removing the multilayered photoresist layer to form a gate connected to the substrate through the second recess structure.
摘要翻译：提供了制造假象高电子迁移率晶体管（PHEMT）的方法。该方法包括以下步骤：制备包括沟道层和作为最上层的覆盖层的衬底; 在封盖层上形成源极和漏极; 在所得结构的整个表面上形成第一保护层，然后图案化第一保护层以暴露沟道区中的覆盖层的一部分; 去除所述覆盖层的暴露部分以形成第一凹陷结构; 在所得结构的整个表面上形成第二保护层，然后构图第二保护层，以暴露第一凹陷结构中的基底的一部分，从而形成第二凹陷结构; 在所得结构的整个表面上形成多层光致抗蚀剂层，然后构图多层光致抗蚀剂层，以通过第二凹陷结构暴露出基板的一部分并形成栅极形开口; 以及沉积金属层以填充所述栅极开口，然后移除所述多层光致抗蚀剂层，以形成通过所述第二凹陷结构连接到所述衬底的栅极。

5. 发明授权

US06940354B2 Microwave power amplifier 有权
标题翻译：微波功率放大器
公开(公告)号：US06940354B2
公开(公告)日：2005-09-06
申请号：US10735037
申请日：2003-12-11
申请人： Dong Min Kang , Hyung Sup Yoon , Hea Cheon Kim , Kyoung Ik Cho
发明人： Dong Min Kang , Hyung Sup Yoon , Hea Cheon Kim , Kyoung Ik Cho
IPC分类号： H03F3/189 , H03F3/60 , H03F3/68 , H03F3/191
CPC分类号： H03F3/605
摘要： A microwave power amplifier comprising a drive amplifying stage includes power elements, gate and drain bias circuits of the power elements, a RC parallel circuit connected between input port and gates of said power elements, a shunt resistor connected between ground terminal and said gates of power elements, and a negative feedback circuit connected in series with resistors and capacitors and in parallel with the power elements. An interstage matching circuit is connected in series with the drive amplifying stage; and a power amplifying stage including power elements connected in parallel with a power divider and a power coupler, gate and drain bias circuits of said power elements, a RC parallel circuit connected between the gates of power elements and the interstage matching circuit, and a shunt resistor connected between a ground and the gates of power elements.
摘要翻译：包括驱动放大级的微波功率放大器包括功率元件，功率元件的栅极和漏极偏置电路，连接在所述功率元件的输入端口和栅极之间的RC并联电路，连接在接地端子和所述功率门之间的分流电阻器元件和与电阻器和电容器串联连接并与功率元件并联的负反馈电路。级间匹配电路与驱动放大级串联; 以及功率放大级，包括与功率分配器和功率耦合器并联连接的功率元件，所述功率元件的栅极和漏极偏置电路，连接在功率元件的栅极和级间匹配电路之间的RC并联电路，以及分流器电阻连接在地和功率元件的门之间。

6. 发明授权

US07387955B2 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US07387955B2
公开(公告)日：2008-06-17
申请号：US11454721
申请日：2006-06-16
申请人： Ho Kyun Ahn , Jong Won Lim , Jae Kyoung Mun , Hong Gu Ji , Woo Jin Chang , Hea Cheon Kim
发明人： Ho Kyun Ahn , Jong Won Lim , Jae Kyoung Mun , Hong Gu Ji , Woo Jin Chang , Hea Cheon Kim
IPC分类号： H01L21/44
CPC分类号： H01L29/812 , H01L29/42316 , H01L29/66462 , H01L29/66856 , H01L29/778
摘要： A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.
摘要翻译：提供具有头部比脚部宽的T形或γ形的精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

7. 发明授权

US07106153B2 Waveguide interconnection apparatus 有权
标题翻译：波导互连设备
公开(公告)号：US07106153B2
公开(公告)日：2006-09-12
申请号：US10788435
申请日：2004-03-01
申请人： Woo Jin Chang , Hea Cheon Kim
发明人： Woo Jin Chang , Hea Cheon Kim
IPC分类号： H01P1/02
CPC分类号： H01P1/022 , H01P1/042
摘要： Provided is a waveguide interconnection apparatus making rectangular interconnecting portions to be a curved structure, whereby it is possible to reduce a signal reflection and a signal loss due to a mismatch occurred from a discontinuous portion where waveguides are perpendicularly connected to each other, and fabricate package products having excellent performances compared to that of the prior art in the same chip and structure.
摘要翻译：提供一种使矩形互连部分成为弯曲结构的波导互连装置，由此可以减少信号反射和由波导彼此垂直连接的不连续部分发生的失配引起的信号丢失，并且制造封装产品在相同的芯片和结构中具有优于现有技术的性能。

8. 发明授权

US06541319B2 Method of manufacturing a self-aligned gate transistor with P-type impurities selectively implanted below the gate, source and drain electrodes 有权
标题翻译：制造具有P型杂质的自对准栅极晶体管的方法，其选择性地注入栅极，源极和漏极之下
公开(公告)号：US06541319B2
公开(公告)日：2003-04-01
申请号：US10032754
申请日：2001-12-26
申请人： Jae Kyoung Mun , Hea Cheon Kim , Jong Won Lim
发明人： Jae Kyoung Mun , Hea Cheon Kim , Jong Won Lim
IPC分类号： H01L21338
CPC分类号： H01L29/66848
摘要： The present invention provides a self-aligned gate transistor. The present invention implants P-type impurity ions only below a channel region below a gate and below a source and drain electrode on semiconductor substrate having an ion implantation channel layer without implanting the P-type impurity ions into a narrow region between the source-gate and the gate-drain, deposits a gate metal and etches the gate pattern. In this case, the length (Lg) of the gate is defined to be narrower than the length (Lch-g) into which P-type impurity ions are implanted below the channel layer, thus improving a pinch-off characteristic. A method of manufacturing a field effect transistor having a self aligned gate according to the present invention comprises the steps of implanting P-type impurity ions only below a channel region below a gate and below a source and drain electrode; and depositing a refractory gate metal having a good high temperature stability to form a gate pattern using a dry etch method.
摘要翻译：本发明提供一种自对准栅极晶体管。本发明仅在栅极下方的沟道区域的下方并且在具有离子注入沟道层的半导体衬底上的源极和漏极电极下方注入P型杂质离子，而不将P型杂质离子注入到源极栅极之间的窄区域并且栅极 - 漏极沉积栅极金属并蚀刻栅极图案。在这种情况下，栅极的长度（Lg）被定义为比在沟道层下方注入P型杂质离子的长度（Lch-g）窄，从而提高夹断特性。根据本发明的制造具有自对准栅极的场效应晶体管的方法包括以下步骤：将P型杂质离子注入仅在栅极下方的沟道区域的下方以及源极和漏极之下; 以及沉积具有良好的高温稳定性的难熔栅极金属，以使用干蚀刻法形成栅极图案。

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