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1. 发明授权

US06741190B2 Method and apparatus for adaptive bus coding for low power deep sub-micron designs 失效
标题翻译：用于低功率深亚微米设计的自适应总线编码的方法和装置
公开(公告)号：US06741190B2
公开(公告)日：2004-05-25
申请号：US10422728
申请日：2003-04-25
申请人： Jörg Henkel , Haris Lekatsas
发明人： Jörg Henkel , Haris Lekatsas
IPC分类号： H03M700
CPC分类号： H04L25/49 , H04L5/20
摘要： The power consumption of interconnects starts to have a significant impact on a system's total power consumption. Besides increasing buses (length, width) etc. this is mostly due to deep sub-micron effects where coupling capacitances between bus lines (wire-to-wire) are in the same order of magnitude as the base capacitances (wire-to-metal-layer). At that point, encoding schemes that solely address the minimization of transitions for the purpose of power reduction do not effectively work any more. Using a physical bus model that accurately models coupling capacitances, a signal bus encoding/decoding apparatus with encoding schemes that are partially adaptive and that take coupling effects into consideration is presented. The encoding schemes do not assume any a priori knowledge that is particular to a specific application.
摘要翻译：互连的功耗开始对系统的总功耗产生重大影响。除了增加总线（长度，宽度）等，这主要是由于深度亚微米效应，其中总线线路（线对线）之间的耦合电容与基极电容（线对金属）相同数量级 -层）。在这一点上，为了减少功率而仅仅解决转换的最小化的编码方案不再有效地起作用。提出了一种准确地模拟耦合电容的物理总线模型，提出了具有部分自适应编码方案的信号总线编码/解码装置，并考虑了耦合效应。编码方案不承担特定应用的任何先验知识。

2. 发明申请

US20060002555A1 Dynamic content-aware memory compression and encryption architecture 失效
公开(公告)号：US20060002555A1
公开(公告)日：2006-01-05
申请号：US10869984
申请日：2004-06-16
申请人： Haris Lekatsas , Joerg Henkel , Srimat Chakradhar , Venkata Jakkula
发明人： Haris Lekatsas , Joerg Henkel , Srimat Chakradhar , Venkata Jakkula
IPC分类号： H04K1/00
CPC分类号： G06F12/0802 , G06F12/121 , G06F2212/401 , Y10S707/99942
摘要： An architecture for content-aware compression and/or encryption of various segments of a application is disclosed. The architecture advantageously allows decompression and decryption units to be placed various levels of a memory hierarchy.

3. 发明授权

US06732256B2 Method and apparatus for object code compression and decompression for computer systems 有权
标题翻译：用于计算机系统的目标代码压缩和解压缩的方法和装置
公开(公告)号：US06732256B2
公开(公告)日：2004-05-04
申请号：US10462675
申请日：2003-06-17
申请人： Jörg Henkel , Wayne Wolf , Haris Lekatsas
发明人： Jörg Henkel , Wayne Wolf , Haris Lekatsas
IPC分类号： G06F930
CPC分类号： G06F9/30178 , G06F9/30156 , G06F9/30185
摘要： A code compression method and apparatus for system-level power optimization that lessens the requirements imposed on main memory size. The apparatus utilizes a post-cache architecture that has a decompression engine that decompresses compressed object code instructions using dictionary look-up tables, branching instruction controllers and mathematical derivations based on bit toggling. The decompression engine extracts the compressed instructions from memory or the instruction/data cache using a bus compression technique to save power as the compressed instructions/data traverses the bus.
摘要翻译：用于系统级功率优化的代码压缩方法和装置，其减轻对主存储器大小的要求。该装置使用具有解压缩引擎的缓存后架构，其使用字典查找表，分支指令控制器和基于位切换的数学推导解压缩压缩目标代码指令。解压缩引擎使用总线压缩技术从存储器或指令/数据高速缓存中提取压缩指令，以在压缩指令/数据穿过总线时节省功率。

4. 发明授权

US07474750B2 Dynamic content-aware memory compression and encryption architecture 失效
标题翻译：动态内容感知内存压缩和加密架构
公开(公告)号：US07474750B2
公开(公告)日：2009-01-06
申请号：US10869984
申请日：2004-06-16
申请人： Haris Lekatsas , Joerg Henkel , Srimat Chakradhar , Venkata Jakkula
发明人： Haris Lekatsas , Joerg Henkel , Srimat Chakradhar , Venkata Jakkula
IPC分类号： H04K1/00
CPC分类号： G06F12/0802 , G06F12/121 , G06F2212/401 , Y10S707/99942
摘要： An architecture for content-aware compression and/or encryption of various segments of a application is disclosed. The architecture advantageously allows decompression and decryption units to be placed various levels of a memory hierarchy.
摘要翻译：公开了一种用于应用的各个段的内容感知压缩和/或加密的架构。该架构有利地允许解压缩和解密单元被放置在存储器层级的各种级别中。

5. 发明申请

US20060101223A1 Compressed memory architecture for embedded systems 失效
标题翻译：嵌入式系统的压缩内存架构
公开(公告)号：US20060101223A1
公开(公告)日：2006-05-11
申请号：US10869985
申请日：2004-06-16
申请人： Haris Lekatsas , Joerg Henkel , Srimat Chakradhar , Venkata Jakkula
发明人： Haris Lekatsas , Joerg Henkel , Srimat Chakradhar , Venkata Jakkula
IPC分类号： G06F12/14
CPC分类号： G06F12/0802 , G06F2212/401 , H03M7/30
摘要： An embedded systems architecture is disclosed which can flexibly handle compression of both instruction code and data.
摘要翻译：公开了可以灵活地处理指令代码和数据的压缩的嵌入式系统架构。

6. 发明申请

US20060069857A1 Compression system and method 审中-公开
标题翻译：压缩系统和方法
公开(公告)号：US20060069857A1
公开(公告)日：2006-03-30
申请号：US11095221
申请日：2005-03-31
申请人： Haris Lekatsas , Joerg Henkel , Venkata Jakkula , Srimat Chakradhar
发明人： Haris Lekatsas , Joerg Henkel , Venkata Jakkula , Srimat Chakradhar
IPC分类号： G06F12/00
CPC分类号： H03M7/30 , H03M7/3084
摘要： A new compression and decompression architecture is herein disclosed which advantageously uses a plurality of parallel content addressable memories of different sizes to perform fast matching during compression.
摘要翻译：本文公开了一种新的压缩和解压缩架构，其有利地使用不同大小的多个并行内容可寻址存储器，以在压缩期间执行快速匹配。

7. 发明申请

US20060005047A1 Memory encryption architecture 审中-公开
标题翻译：内存加密架构
公开(公告)号：US20060005047A1
公开(公告)日：2006-01-05
申请号：US10869983
申请日：2004-06-16
申请人： Haris Lekatsas , Joerg Henkel , Srimat Chakradhar , Venkata Jakkula
发明人： Haris Lekatsas , Joerg Henkel , Srimat Chakradhar , Venkata Jakkula
IPC分类号： G06F11/30
CPC分类号： G06F12/1408 , G06F12/0875 , G06F21/79 , G06F21/85 , G06F2212/401
摘要： A system architecture is disclosed that can support fast random access to encrypted memory.
摘要翻译：公开了可以支持对加密存储器的快速随机访问的系统架构。

8. 发明授权

US06892292B2 Apparatus for one-cycle decompression of compressed data and methods of operation thereof 失效
标题翻译：用于压缩数据的一周期解压缩的装置及其操作方法
公开(公告)号：US06892292B2
公开(公告)日：2005-05-10
申请号：US10135575
申请日：2002-05-01
申请人： Joerg Henkel , Haris Lekatsas , Venkata Jakkula
发明人： Joerg Henkel , Haris Lekatsas , Venkata Jakkula
IPC分类号： G06F5/00 , G06F9/30 , G06F9/318
CPC分类号： G06F9/30178
摘要： Code compression is known as an effective technique to reduce instruction memory size on an embedded system. However, code compression can also be very effective in increasing the processor-to-memory bandwidth and hence provide increased system performance. A code decompression engine having plurality of dictionary tables, coupled with decoding circuitry and appropriate control circuitry, is coupled between the processor core and the instruction cache. The code decompression engine provides one-cycle decompression of compressed instructions that are intermixed with uncompressed instructions, thereby increasing processor-to-memory bandwidth and avoiding processor stalls.
摘要翻译：已知代码压缩是减少嵌入式系统指令存储器大小的有效技术。然而，代码压缩在提高处理器到存储器带宽方面也是非常有效的，因此提供了增加的系统性能。具有与解码电路和适当控制电路耦合的多个字典表的代码解压缩引擎耦合在处理器核心和指令高速缓存之间。代码解压缩引擎提供与未压缩指令混合的压缩指令的一周期解压缩，从而增加处理器到存储器的带宽并避免处理器停顿。

9. 发明授权

US06691305B1 Object code compression using different schemes for different instruction types 有权
标题翻译：使用不同方案的对象代码压缩用于不同的指令类型
公开(公告)号：US06691305B1
公开(公告)日：2004-02-10
申请号：US09556927
申请日：2000-04-21
申请人： Jörg Henkel , Wayne Wolf , Haris Lekatsas
发明人： Jörg Henkel , Wayne Wolf , Haris Lekatsas
IPC分类号： G06F945
CPC分类号： G06F9/30178 , G06F9/30156 , G06F9/30185
摘要： A code compression method for system-level power optimization that lessens the requirements imposed on main memory size. The method reduces the power consumption of a complete system comprising a CPU, instruction cache, data cache, main memory, data buses and address bus. The method includes extracting compressible instruction and data portions from executable code, creating a mathematical model of the extracted code portions, class the individual instructions in the extracted portions based upon their operation codes and compressing the instructions. The compressed instructions are further compressed when extracted from memory by using bus compaction. The method is also embodied in a computer system with a processor and a memory adapted to perform the steps of the method to compress the extracted instruction portions. Additionally, the method is embodied on a computer program product bearing software instructions adapted to perform the steps of the method to compress the extracted instruction portions. The invention also has an apparatus utilizing a post-cache architecture that has a decompression engine that decompresses instructions that have been compressed using the method of the invention. The apparatus extracts the compressed instructions from memory or the instruction/data cache using a bus compression technique to save power as the compressed instructions/data traverses the bus.
摘要翻译：用于系统级功率优化的代码压缩方法，可减轻对主内存大小的要求。该方法降低了包括CPU，指令高速缓存，数据高速缓存，主存储器，数据总线和地址总线的完整系统的功耗。该方法包括从可执行代码提取可压缩指令和数据部分，创建提取的代码部分的数学模型，根据它们的操作代码对压缩指令进行分类，提取部分中的各个指令。当通过使用总线压缩从存储器中提取时，压缩指令进一步被压缩。该方法还体现在具有处理器和存储器的计算机系统中，适于执行压缩提取的指令部分的方法的步骤。此外，该方法体现在一种计算机程序产品上，该计算机程序产品具有适于执行压缩所提取的指令部分的方法的步骤的软件指令。本发明还具有使用具有解压缩引擎的缓存后结构的装置，该解压缩引擎使用本发明的方法对已经被压缩的指令进行解压缩。该装置使用总线压缩技术从存储器或指令/数据高速缓存中提取压缩指令，以在压缩指令/数据穿过总线时节省功率。

10. 发明授权

US06583735B2 Method and apparatus for adaptive bus coding for low power deep sub-micron designs 失效
标题翻译：用于低功率深亚微米设计的自适应总线编码的方法和装置
公开(公告)号：US06583735B2
公开(公告)日：2003-06-24
申请号：US09920854
申请日：2001-08-03
申请人： Jörg Henkel , Haris Lekatsas
发明人： Jörg Henkel , Haris Lekatsas
IPC分类号： H03M734
CPC分类号： H04L25/49 , H04L5/20
摘要： The power consumption of interconnects starts to have a significant impact on a system's total power consumption. Besides increasing buses (length, width) etc. this is mostly due to deep sub-micron effects where coupling capacitances between bus lines (wire-to-wire) are in the same order of magnitude as the base capacitances (wire-to-metal-layer). At that point, encoding schemes that solely address the minimization of transitions for the purpose of power reduction do not effectively work any more. Using a physical bus model that accurately models coupling capacitances, a signal bus encoding/decoding apparatus with encoding schemes that are partially adaptive and that take coupling effects into consideration is presented. The encoding schemes do not assume any a priori knowledge that is particular to a specific application.
摘要翻译：互连的功耗开始对系统的总功耗产生重大影响。除了增加总线（长度，宽度）等，这主要是由于深度亚微米效应，其中总线线路（线对线）之间的耦合电容与基极电容（线对金属）相同数量级 -层）。在这一点上，为了减少功率而仅仅解决转换的最小化的编码方案不再有效地起作用。提出了一种准确地模拟耦合电容的物理总线模型，提出了具有部分自适应编码方案的信号总线编码/解码装置，并考虑了耦合效应。编码方案不承担特定应用的任何先验知识。

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