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1. 发明授权

US09501407B1 First-in-first-out memory with dual memory banks 有权
标题翻译：先进先出的双存储器存储器
公开(公告)号：US09501407B1
公开(公告)日：2016-11-22
申请号：US13235228
申请日：2011-09-16
申请人： Ray Ruey-Hsien Hu , Andy L. Lee , David Lewis , Tony Ngai , Haiming Yu , Hao-Yuan Howard Chou
发明人： Ray Ruey-Hsien Hu , Andy L. Lee , David Lewis , Tony Ngai , Haiming Yu , Hao-Yuan Howard Chou
IPC分类号： G06F12/06 , G06F13/16
CPC分类号： G06F12/0607 , G06F13/1689 , Y02D10/14
摘要： A first-in-first-out memory may have first and second memory banks. A write controller may write data into the first and second memory banks. In performing write operations, the write controller may determine whether to write the data into the first bank or the second bank by evaluating a first bank empty flag and a second bank empty flag. When transitioning between writing in the first bank and the second bank, the write controller may latch a write address value indicative of the last location at which valid data was written in a given bank. A read controller may read data from the first and second memory bank. The read controller may determine when to transition between reading in the first bank and reading in the second bank by comparing a current read address to the latched write address value.
摘要翻译：先入先出的存储器可以具有第一和第二存储体。写控制器可以将数据写入第一和第二存储体。在执行写入操作时，写入控制器可以通过评估第一存储体空标志和第二存储体空标志来确定是否将数据写入第一存储体或第二存储体。当在第一组和第二组中的写入之间转换时，写入控制器可以锁存指示在给定存储体中写入有效数据的最后位置的写入地址值。读取控制器可以从第一和第二存储体读取数据。读取控制器可以通过将当前读取地址与锁存的写入地址值进行比较来确定何时在第一存储区中的读取和第二存储区中的读取之间转换。

2. 发明申请

US20130073763A1 MEMORY ARBITRATION CIRCUITRY 有权
标题翻译：内存仲裁电路
公开(公告)号：US20130073763A1
公开(公告)日：2013-03-21
申请号：US13234925
申请日：2011-09-16
申请人： Ray Ruey-Hsien Hu , Haiming Yu , Hao-Yuan Howard Chou
发明人： Ray Ruey-Hsien Hu , Haiming Yu , Hao-Yuan Howard Chou
IPC分类号： G06F13/362
CPC分类号： G11C7/1075
摘要： An integrated circuit with memory elements is provided. The memory elements may be single-port memory cells that are used to provide multiport memory functionality. The integrated circuit may include an arbitration circuit operable to receive memory access requests from at least first and second request generators. The arbitration circuit may be configured to operate in a synchronous mode and an asynchronous mode. The arbitration circuit operating in the synchronous mode may perform port selection based on a predetermined logic table. The arbitration circuit operating in the asynchronous mode may execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed.
摘要翻译：提供了一种具有存储元件的集成电路。存储器元件可以是用于提供多端口存储器功能的单端口存储器单元。集成电路可以包括可操作以从至少第一和第二请求发生器接收存储器访问请求的仲裁电路。仲裁电路可以被配置为以同步模式和异步模式操作。以同步模式工作的仲裁电路可以基于预定的逻辑表执行端口选择。以异步模式工作的仲裁电路一旦被仲裁电路接收到就可以执行存储器请求。正在执行当前存储器访问时接收的请求可以被保持，直到当前存储器访问已经完成。

3. 发明授权

US09256266B1 Negative bit line driver circuitry 有权
标题翻译：负位线驱动电路
公开(公告)号：US09256266B1
公开(公告)日：2016-02-09
申请号：US13289953
申请日：2011-11-04
申请人： Haiming Yu , Wei Zhang , Hao-Yuan Howard Chou , Ray Ruey-Hsien Hu
发明人： Haiming Yu , Wei Zhang , Hao-Yuan Howard Chou , Ray Ruey-Hsien Hu
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3296 , Y02D10/172
摘要： Integrated circuits with memory elements are provided. Data may be loaded into the memory elements using write driver circuitry. The write driver circuitry may be provided with a fixed positive power supply voltage and an time-varying ground power supply voltage that is less than the positive power supply voltage. The time-varying ground power supply voltage may be generated using programmable power supply circuitry. The programmable power supply circuitry may include a pulse generation circuit and a configurable capacitive circuit. The pulse generation circuit may output a pulse signal to the capacitive circuit. In response to receiving the pulse signal, the capacitive circuit may push the time-varying ground power supply voltage to a negative value. The time-varying ground power supply voltage may be driven below zero volts for at least a portion of a write cycle to help improve write margins and increase memory yield.
摘要翻译：提供具有存储元件的集成电路。可以使用写入驱动器电路将数据加载到存储器元件中。写驱动器电路可以具有小于正电源电压的固定正电源电压和时变接地电源电压。可以使用可编程电源电路产生时变接地电源电压。可编程电源电路可以包括脉冲发生电路和可配置电容电路。脉冲发生电路可以向电容电路输出脉冲信号。响应于接收脉冲信号，电容电路可以将时变接地电源电压推到负值。对于写周期的至少一部分，时变接地电源电压可以被驱动到低于零伏特，以帮助改善写入裕度并增加存储器产量。

4. 发明授权

US08867303B2 Memory arbitration circuitry 有权
标题翻译：内存仲裁电路
公开(公告)号：US08867303B2
公开(公告)日：2014-10-21
申请号：US13234925
申请日：2011-09-16
申请人： Ray Ruey-Hsien Hu , Haiming Yu , Hao-Yuan Howard Chou
发明人： Ray Ruey-Hsien Hu , Haiming Yu , Hao-Yuan Howard Chou
IPC分类号： G11C8/00 , G11C7/10
CPC分类号： G11C7/1075
摘要： An integrated circuit with memory elements is provided. The memory elements may be single-port memory cells that are used to provide multiport memory functionality. The integrated circuit may include an arbitration circuit operable to receive memory access requests from at least first and second request generators. The arbitration circuit may be configured to operate in a synchronous mode and an asynchronous mode. The arbitration circuit operating in the synchronous mode may perform port selection based on a predetermined logic table. The arbitration circuit operating in the asynchronous mode may execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed.
摘要翻译：提供了一种具有存储元件的集成电路。存储器元件可以是用于提供多端口存储器功能的单端口存储器单元。集成电路可以包括可操作以从至少第一和第二请求发生器接收存储器访问请求的仲裁电路。仲裁电路可以被配置为以同步模式和异步模式操作。以同步模式工作的仲裁电路可以基于预定的逻辑表执行端口选择。以异步模式工作的仲裁电路一旦被仲裁电路接收到就可以执行存储器请求。正在执行当前存储器访问时接收的请求可以被保持，直到当前存储器访问已经完成。

5. 发明授权

US08483006B1 Programmable addressing circuitry for increasing memory yield 有权
标题翻译：可编程寻址电路，用于提高内存产量
公开(公告)号：US08483006B1
公开(公告)日：2013-07-09
申请号：US13234990
申请日：2011-09-16
申请人： Hao-Yuan Howard Chou , Wei Zhang , Haiming Yu
发明人： Hao-Yuan Howard Chou , Wei Zhang , Haiming Yu
IPC分类号： G11C8/00 , G11C11/00 , G11C5/14
CPC分类号： G11C11/418 , G11C11/412
摘要： Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. The access transistors may have gates that are controlled by an address signal. The address signal may be asserted during read/write operations to turn on the access transistors so that read/write data can be passed through the access transistors. The voltage level to which the address signal is raised during read/write operations may be adjusted using programmable voltage biasing circuitry. A number of integrated circuits may be tested during device characterization procedures to determine the amount by which the address signal should be adjusted using the programmable voltage biasing circuit so that the memory elements in the integrated circuits satisfy design criteria.
摘要翻译：提供具有存储元件的集成电路。存储元件可以包括通过存取晶体管耦合到数据线的存储电路。存取晶体管可以具有由地址信号控制的栅极。在读/写操作期间可以断言地址信号以接通存取晶体管，使得读/写数据可以通过存取晶体管。可以使用可编程电压偏置电路来调整在读/写操作期间提高地址信号的电压电平。可以在器件表征过程期间测试多个集成电路，以确定使用可编程电压偏置电路来调整地址信号的量，使得集成电路中的存储元件满足设计标准。

6. 发明授权

US07639557B1 Configurable random-access-memory circuitry 有权
标题翻译：可配置的随机存取存储器电路
公开(公告)号：US07639557B1
公开(公告)日：2009-12-29
申请号：US11714327
申请日：2007-03-05
申请人： Hao-Yuan Howard Chou , Haiming Yu
发明人： Hao-Yuan Howard Chou , Haiming Yu
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , H03K19/1776 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays that may be configured for true dual port operation or simple dual port operation. The memory arrays include memory cells arranged in rows and columns and associated row address lines and data lines. Sense amplifiers and write drivers are used for reading and writing data. Precharge drivers are used to precharge the data lines prior to read operations. Configurable multiplexer circuitry in the array has read paths through which data is provided to the sense amplifiers from the memory cells. The multiplexer circuitry has write paths through which data from the write drivers is written into the memory cells. The read paths and the write paths contain no more than a single pass gate each. Each precharge driver may be connected to a respective one of the data lines with no intervening pass gates.
摘要翻译：提供了诸如可编程逻辑器件集成电路的集成电路，其具有可被配置用于真正双端口操作或简单双端口操作的存储器阵列。存储器阵列包括排列成行和列的存储单元以及相关联的行地址线和数据线。感应放大器和写入驱动器用于读取和写入数据。预充电驱动器用于在读取操作之前预充电数据线。阵列中的可配置多路复用器电路具有从存储器单元向读出放大器提供数据的读取路径。多路复用器电路具有写入路径，来自写入驱动器的数据通过该路径被写入存储器单元。读取路径和写入路径每个不包含单个传递门。每个预充电驱动器可以连接到相应的一条数据线，而没有中间通路门。

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