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1. 发明授权

US4765865A Silicon etch rate enhancement 失效
标题翻译：硅蚀刻速率增强
公开(公告)号：US4765865A
公开(公告)日：1988-08-23
申请号：US45658
申请日：1987-05-04
申请人： Roy L. Gealer , Hans K. Karsten
发明人： Roy L. Gealer , Hans K. Karsten
IPC分类号： H01L21/306 , H01L21/3063 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/3063 , H01L21/30608 , Y10T428/12528 , Y10T428/24331
摘要： This invention is directed to a method for increasing the etch rate of a single crystal silicon wafer in an anisotropic etching solution. This method comprises applying a mask material to a portion of one face of the wafer and a metal coating to substantially the entire surface of an opposite face of the wafer which renders the electrode potential of the masked, metal coated single crystal silicon wafer more anodic than that of a masked, single crystal silicon wafer alone, and exposing the coated wafer to a suitable anisotropic etching solution. This method may further comprise applying an external anodic voltage to the masked, metal coated single crystal silicon wafer, which voltage is less than that which causes the electrode potential of the masked, metal coated single crystal silicon wafer to exceed the passivation potential of the masked, single crystal silicon wafer.
摘要翻译：本发明涉及一种用于提高各向异性蚀刻溶液中单晶硅晶片的蚀刻速率的方法。该方法包括将掩模材料施加到晶片的一个面的一部分上，并将金属涂层施加到晶片的相对表面的基本上整个表面，使得被掩蔽的金属涂覆的单晶硅晶片的电极电位比阳极更加阳极，单独的掩模的单晶硅晶片，并将涂覆的晶片暴露于合适的各向异性蚀刻溶液。该方法可以进一步包括将外部阳极电压施加到被掩蔽的金属涂覆的单晶硅晶片，该电压小于使被掩蔽的金属涂覆的单晶硅晶片的电极电位超过被掩蔽的金属涂覆的单晶硅晶片的钝化电位，单晶硅晶片。

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