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1. 发明申请

US20130109173A1 METHODS FOR REMOVING SILICON NITRIDE SPACER, FORMING TRANSISTOR AND FORMING SEMICONDUCTOR DEVICES 审中-公开
标题翻译：移除硅酸盐隔离膜，形成晶体管和成型半导体器件的方法
公开(公告)号：US20130109173A1
公开(公告)日：2013-05-02
申请号：US13357613
申请日：2012-01-24
申请人： HUANXIN LIU
发明人： HUANXIN LIU
IPC分类号： H01L21/28
CPC分类号： H01L29/66507 , H01L21/28518 , H01L21/823412 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L29/7833 , H01L29/7843
摘要： A method for removing silicon nitride spacers includes providing a silicon substrate having a gate formed thereon, silicon nitride spacers formed on sidewalls of the gate, and source/drain regions formed in the silicon substrate on both sides of the gate, forming metal layers on the gate and the source/drain regions, and performing a first annealing process in which the metal layers react with the silicon substrate so as to form first metal silicide layers. The method further includes forming protective layers on the first metal silicide layers, placing the silicon substrate into a phosphorous acid solution saturated with silicon ions so as to remove the silicon nitride spacers, and after removing the silicon nitride spacers, performing a second annealing process in which the first metal silicide layers react with the silicon substrate so as to form second metal silicide layers.
摘要翻译：一种用于去除氮化硅间隔物的方法包括提供其上形成有栅极的硅衬底，形成在栅极侧壁上的氮化硅间隔物和形成在栅极两侧的硅衬底中的源极/漏极区，在栅极的两侧形成金属层栅极和源极/漏极区域，并且执行其中金属层与硅衬底反应以形成第一金属硅化物层的第一退火工艺。该方法还包括在第一金属硅化物层上形成保护层，将硅衬底置于用硅离子饱和的亚磷酸溶液中以除去氮化硅间隔物，在除去氮化硅间隔物之后，进行第二退火处理第一金属硅化物层与硅衬底反应以形成第二金属硅化物层。

2. 发明授权

US08912568B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08912568B2
公开(公告)日：2014-12-16
申请号：US13354060
申请日：2012-01-19
申请人： Huanxin Liu , Huojin Tu
发明人： Huanxin Liu , Huojin Tu
IPC分类号： H01L21/205 , H01L29/12 , H01L21/306 , H01L29/78 , H01L21/02 , H01L29/04 , H01L21/308
CPC分类号： H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02532 , H01L21/02639 , H01L21/02658 , H01L21/30608 , H01L21/3083 , H01L29/045 , H01L29/7848
摘要： A semiconductor device and manufacturing method therefor includes a Σ-shaped embedded source or drain regions. A U-shaped recess is formed in a Si substrate using dry etching and a SiGe layer is grown epitaxially on the bottom of the U-shaped recess. Using an orientation selective etchant having a higher etching rate with respect to Si than SiGe, wet etching is performed on the Si substrate sidewalls of the U-shaped recess, to form a Σ-shaped recess.
摘要翻译：一种半导体器件及其制造方法包括一个嵌入式的源极或漏极区域。使用干蚀刻在Si衬底中形成U形凹部，并且在U形凹部的底部上外延生长SiGe层。使用相对于SiGe具有比Si更高的蚀刻速率的取向选择性蚀刻剂，对U形凹部的Si衬底侧壁进行湿蚀刻，以形成“S”形凹槽。

3. 发明申请

US20130040462A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130040462A1
公开(公告)日：2013-02-14
申请号：US13310624
申请日：2011-12-02
申请人： HUANXIN LIU
发明人： HUANXIN LIU
IPC分类号： H01L21/306
CPC分类号： H01L21/3083 , H01L21/02238 , H01L21/30608 , H01L29/66636 , H01L29/7848
摘要： A method of fabricating a semiconductor device for improving the performance of “Σ” shaped embedded source/drain regions is disclosed. A “U” shaped recess is formed in a Si substrate. The recess is treated with a surfactant, the amount of surfactant adsorbed on the recess sidewalls being greater than that on the recess bottom. An oxide is formed on the bottom. The presence of surfactant on the sidewalls, prevents oxide from forming thereon. The surfactant on the sidewalls is then removed and an orientation selective wet etching process is performed on the sidewalls. The oxide protects the Si at the bottom is from being etched.
摘要翻译：一种制造用于提高“Sgr”性能的半导体器件的方法。形状的嵌入式源极/漏极区域被公开。在Si衬底中形成U形凹部。用表面活性剂处理凹槽，吸附在凹陷侧壁上的表面活性剂的量大于凹槽底部的表面活性剂的量。在底部形成氧化物。在侧壁上存在表面活性剂，防止在其上形成氧化物。然后去除侧壁上的表面活性剂，并在侧壁上进行取向选择性湿蚀刻工艺。氧化物保护底部的Si不被蚀刻。

4. 发明授权

US08372722B2 Method for fabricating a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08372722B2
公开(公告)日：2013-02-12
申请号：US13290007
申请日：2011-11-04
申请人： Qingsong Wei , Yonggen He , Huanxin Liu , Jialei Liu , Chaowei Li
发明人： Qingsong Wei , Yonggen He , Huanxin Liu , Jialei Liu , Chaowei Li
IPC分类号： H01L21/336
CPC分类号： H01L21/26533 , H01L21/30617 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of fabricating semiconductor device includes forming a recess having a substantially rectangular section and forming an oxide layer on sidewalls and an oxide layer on a bottom of the recess by anisotropic oxidation, wherein the oxide layer on the sidewalls is thinner than the oxide layer on the bottom of recess. The method further includes completely removing the oxide layer on the sidewalls and partially removing the oxide layer on the bottom of the recess. The method also includes performing an orientation selective wet etching on the recess using a remaining oxide layer of the recess as a stop layer to shape the sidewalls into a Σ shaped section. The method includes removing the remaining oxide layer using an isotropic wet etching.
摘要翻译：一种制造半导体器件的方法包括：形成具有基本矩形部分的凹槽，并通过各向异性氧化在侧壁上形成氧化物层和位于凹陷底部的氧化物层，其中侧壁上的氧化物层比氧化物层薄底部的凹槽。该方法还包括完全去除侧壁上的氧化物层，并部分去除凹部底部的氧化物层。所述方法还包括使用所述凹部的剩余氧化物层作为停止层来在所述凹部上执行取向选择性湿蚀刻，以将所述侧壁成形为“ 形截面。该方法包括使用各向同性湿蚀刻去除剩余的氧化物层。

5. 发明申请

US20130017661A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130017661A1
公开(公告)日：2013-01-17
申请号：US13290007
申请日：2011-11-04
申请人： QINGSONG WEI , YONGGEN He , HUANXIN Liu , Jialei Liu , Chaowei Li
发明人： QINGSONG WEI , YONGGEN He , HUANXIN Liu , Jialei Liu , Chaowei Li
IPC分类号： H01L21/336
CPC分类号： H01L21/26533 , H01L21/30617 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of fabricating semiconductor device includes forming a recess having a substantially rectangular section and forming an oxide layer on sidewalls and an oxide layer on a bottom of the recess by anisotropic oxidation, wherein the oxide layer on the sidewalls is thinner than the oxide layer on the bottom of recess. The method further includes completely removing the oxide layer on the sidewalls and partially removing the oxide layer on the bottom of the recess. The method also includes performing an orientation selective wet etching on the recess using a remaining oxide layer of the recess as a stop layer to shape the sidewalls into a Σ shaped section. The method includes removing the remaining oxide layer using an isotropic wet etching.
摘要翻译：一种制造半导体器件的方法包括：形成具有基本上矩形部分的凹槽，并通过各向异性氧化在侧壁上形成氧化物层和凹陷底部的氧化物层，其中侧壁上的氧化物层比氧化物层薄底部的凹槽。该方法还包括完全去除侧壁上的氧化物层，并部分去除凹部底部的氧化物层。所述方法还包括使用所述凹部的剩余氧化物层作为停止层来在所述凹部上执行取向选择性湿蚀刻，以将所述侧壁成形为“ 形截面。该方法包括使用各向同性湿蚀刻去除剩余的氧化物层。

6. 发明申请

US20120319168A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120319168A1
公开(公告)日：2012-12-20
申请号：US13354060
申请日：2012-01-19
申请人： Huanxin Liu , Huojin Tu
发明人： Huanxin Liu , Huojin Tu
IPC分类号： H01L21/205 , H01L29/12 , B82Y40/00 , B82Y99/00
CPC分类号： H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02532 , H01L21/02639 , H01L21/02658 , H01L21/30608 , H01L21/3083 , H01L29/045 , H01L29/7848
摘要： A semiconductor device and manufacturing method therefor includes a Σ-shaped embedded source or drain regions. A U-shaped recess is formed in a Si substrate using dry etching and a SiGe layer is grown epitaxially on the bottom of the U-shaped recess. Using an orientation selective etchant having a higher etching rate with respect to Si than SiGe, wet etching is performed on the Si substrate sidewalls of the U-shaped recess, to form a Σ-shaped recess.
摘要翻译：一种半导体器件及其制造方法包括一个嵌入式的源极或漏极区域。使用干蚀刻在Si衬底中形成U形凹部，并且在U形凹部的底部上外延生长SiGe层。使用相对于SiGe具有比Si更高的蚀刻速率的取向选择性蚀刻剂，对U形凹部的Si衬底侧壁进行湿蚀刻，以形成“S”形凹槽。

7. 发明授权

US08580695B2 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08580695B2
公开(公告)日：2013-11-12
申请号：US13310624
申请日：2011-12-02
申请人： Huanxin Liu
发明人： Huanxin Liu
IPC分类号： H01L21/302
CPC分类号： H01L21/3083 , H01L21/02238 , H01L21/30608 , H01L29/66636 , H01L29/7848
摘要： A method of fabricating a semiconductor device for improving the performance of “Σ” shaped embedded source/drain regions is disclosed. A “U” shaped recess is formed in a Si substrate. The recess is treated with a surfactant, the amount of surfactant adsorbed on the recess sidewalls being greater than that on the recess bottom. An oxide is formed on the bottom. The presence of surfactant on the sidewalls, prevents oxide from forming thereon. The surfactant on the sidewalls is then removed and an orientation selective wet etching process is performed on the sidewalls. The oxide protects the Si at the bottom is from being etched.
摘要翻译：公开了制造用于提高“Sigma”形嵌入式源/漏区的性能的半导体器件的方法。在“硅”衬底中形成“U”形凹槽。用表面活性剂处理凹槽，吸附在凹陷侧壁上的表面活性剂的量大于凹槽底部的表面活性剂的量。在底部形成氧化物。在侧壁上存在表面活性剂，防止在其上形成氧化物。然后去除侧壁上的表面活性剂，并在侧壁上进行取向选择性湿蚀刻工艺。氧化物保护底部的Si不被蚀刻。

8. 发明授权

US08377770B2 Method for manufacturing transistor 有权
标题翻译：晶体管制造方法
公开(公告)号：US08377770B2
公开(公告)日：2013-02-19
申请号：US13305726
申请日：2011-11-28
申请人： Huanxin Liu
发明人： Huanxin Liu
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807
摘要： A method for manufacturing a semiconductor device includes providing a substrate having an NMOS transistor and a PMOS transistor formed thereon, forming a stressed layer that covers the transistors, and selectively removing the stressed layer on the PMOS transistor. The method further includes annealing the substrate, removing the remaining stressed layer, forming a dielectric layer structure on the transistors; and performing a first planarization process on the dielectric layer structure. The method also includes forming a corrosion-resistant insulating structure on a rear surface of the substrate, and performing a second planarization process on the dielectric layer structure. The semiconductor device thus formed can withstand high voltages while maintaining gate oxide integrity.
摘要翻译：一种制造半导体器件的方法包括提供一种具有形成在其上的NMOS晶体管和PMOS晶体管的衬底，形成覆盖晶体管的应力层，以及选择性地去除PMOS晶体管上的应力层。该方法还包括退火衬底，去除剩余的应力层，在晶体管上形成介电层结构; 对介质层结构进行第一平面化处理。该方法还包括在基板的后表面上形成耐腐蚀的绝缘结构，并对介电层结构进行第二平面化处理。这样形成的半导体器件可以承受高电压同时保持栅极氧化物的完整性。

9. 发明申请

US20130015443A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130015443A1
公开(公告)日：2013-01-17
申请号：US13291088
申请日：2011-11-07
申请人： YONGGEN HE , Bing Wu , Huanxin Liu
发明人： YONGGEN HE , Bing Wu , Huanxin Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/02532 , H01L21/02579 , H01L21/02639 , H01L21/2658 , H01L21/30608 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method for manufacturing a semiconductor device comprises: forming a recess in a substrate; implanting at the bottom of the recess to form an amorphous layer to a predetermined depth under the bottom of the recess; carrying out crystal orientation selective wet etching to form a Sigma shaped recess by use of the amorphous layer as a stopping layer. Through forming an amorphous layer by means of implantation which is used as a stopping layer in a subsequent wet etching, a Sigma shaped recess with a cuspate bottom is avoided, and a Sigma shaped recess having a planar bottom is obtained, which may further improve semiconductor device performance.
摘要翻译：一种制造半导体器件的方法包括：在衬底中形成凹陷; 植入在所述凹部的底部以在所述凹部的底部下方形成非晶层至预定深度; 通过使用非晶层作为停止层，进行晶体取向选择性湿蚀刻以形成Sigma形凹部。通过在随后的湿式蚀刻中用作停止层的注入形成非晶层，避免了具有尖端底部的Sigma形凹槽，并且获得具有平坦底部的Sigma形凹部，这可以进一步改善半导体设备性能。

10. 发明申请

US20120214295A1 METHOD FOR MANUFACTURING TRANSISTOR 有权
标题翻译：制造晶体管的方法
公开(公告)号：US20120214295A1
公开(公告)日：2012-08-23
申请号：US13305726
申请日：2011-11-28
申请人： HUANXIN LIU
发明人： HUANXIN LIU
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/823807
摘要： A method for manufacturing a semiconductor device includes providing a substrate having an NMOS transistor and a PMOS transistor formed thereon, forming a stressed layer that covers the transistors, and selectively removing the stressed layer on the PMOS transistor. The method further includes annealing the substrate, removing the remaining stressed layer, forming a dielectric layer structure on the transistors; and performing a first planarization process on the dielectric layer structure. The method also includes forming a corrosion-resistant insulating structure on a rear surface of the substrate, and performing a second planarization process on the dielectric layer structure. The semiconductor device thus formed can withstand high voltages while maintaining gate oxide integrity.
摘要翻译：一种制造半导体器件的方法包括提供一种具有形成在其上的NMOS晶体管和PMOS晶体管的衬底，形成覆盖晶体管的应力层，以及选择性地去除PMOS晶体管上的应力层。该方法还包括退火衬底，去除剩余的应力层，在晶体管上形成介电层结构; 对介质层结构进行第一平面化处理。该方法还包括在基板的后表面上形成耐腐蚀的绝缘结构，并对介电层结构进行第二平面化处理。这样形成的半导体器件可以承受高电压同时保持栅极氧化物的完整性。

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