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1. 发明授权

US5434592A Multimedia expansion unit 失效
标题翻译：多媒体扩展单元
公开(公告)号：US5434592A
公开(公告)日：1995-07-18
申请号：US122819
申请日：1993-09-17
申请人： John M. Dinwiddie, Jr. , Bobby J. Freeman , Thomas J. Micallef , Gustavo A. Suarez , Bruce J. Wilkie
发明人： John M. Dinwiddie, Jr. , Bobby J. Freeman , Thomas J. Micallef , Gustavo A. Suarez , Bruce J. Wilkie
IPC分类号： G09G5/00 , G06F3/14 , G06T3/00 , G09G5/14 , H04N5/765 , G09G1/14
CPC分类号： H04N21/4143 , G06F3/14 , G09G5/14 , H04N5/765 , G09G2340/125
摘要： A multimedia solution is presented which allows a multimedia architecture to be implemented on an existing computer system. According to the invention, an expansion unit which incorporates a multimedia architecture is provided. The expansion unit is connected to an existing computer system via an expansion slot of an I/O bus of the existing computer as well as via a display device output terminal of the computer. The expansion unit is also connected to a display device. Accordingly, the expansion unit controls the presentation which is provided on the display device.
摘要翻译：提出了一种多媒体解决方案，允许在现有计算机系统上实现多媒体架构。根据本发明，提供了一种结合多媒体架构的扩展单元。扩展单元通过现有计算机的I / O总线的扩展槽以及计算机的显示设备输出端连接到现有的计算机系统。扩展单元也连接到显示设备。因此，扩展单元控制在显示装置上提供的呈现。

2. 发明授权

US5245322A Bus architecture for a multimedia system 失效
标题翻译：多媒体系统的总线架构
公开(公告)号：US5245322A
公开(公告)日：1993-09-14
申请号：US625577
申请日：1990-12-11
申请人： John M. Dinwiddie, Jr. , Bobby J. Freeman , Gustavo A. Suarez , Bruce J. Wilkie
发明人： John M. Dinwiddie, Jr. , Bobby J. Freeman , Gustavo A. Suarez , Bruce J. Wilkie
IPC分类号： G06F13/10 , G06F3/14 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/14 , G09G5/36 , G09G5/39 , H04N5/222 , H04N5/265
CPC分类号： G09G5/36 , G06F3/14 , G09G5/026 , G09G5/14 , H04N5/222 , G09G1/167 , G09G2340/125
摘要： An information handling apparatus for transferring and composing image signals for display. The apparatus includes a bus adapted to allow selective access for multiple independent image signals generated by respective independent image sources. The selective access enables composition of the independent image signals in response to control information; the composition enables real time display of a composed image signal.

3. 发明授权

US5175731A Arbitration circuit for a multimedia system 失效
标题翻译：多媒体系统的仲裁电路
公开(公告)号：US5175731A
公开(公告)日：1992-12-29
申请号：US626792
申请日：1990-12-11
申请人： Gustavo A. Suarez
发明人： Gustavo A. Suarez
IPC分类号： G06F13/42 , G06F3/14 , G06F13/374 , G09G1/16 , G09G5/14
CPC分类号： G09G5/14 , G06F13/374 , G06F3/14 , G09G1/167 , G09G2340/125
摘要： The invention is an N-bit arbitration circuit which includes N bit subcircuits, each of which provides a single bit output signal of an N-bit arbitration signal. The bit subcircuits include a more significant bit subcircuit and at least significant bit subcircuit. The more significant bit subcircuit includes a gate, which receives a more significant bit priority signal and an arbitration enable signal and provides a more significant bit output of the N-bit arbitration signal, and a pipeline circuit, which receives the more significant bit priority signal, the arbitration enable signal and the more significant bit output and provides a pipelined arbitration enable signal based upon the more significant bit priority signal, the arbitration enable signal and the more significant bit. The least significant bit subcircuit includes a gate, which receives a least significant bit priority signal and the pipelined arbitration enable signal and provides a least significant bit output signal of the N-bit arbitration circuit output signal, and a source enable circuit, which receives the least significant bit arbitration enable signal, the priority signal and the pipelined arbitration enable signal and provides a source enable signal based upon the least significant bit arbitration indication signal and the pipelined arbitration signal.

4. 发明授权

US5508734A Method and apparatus for hemispheric imaging which emphasizes peripheral content 失效
标题翻译：用于半球成像的方法和装置，其强调外围内容
公开(公告)号：US5508734A
公开(公告)日：1996-04-16
申请号：US281331
申请日：1994-07-27
申请人： Robert G. Baker , Kevin Kettler , Gustavo A. Suarez , Kenneth A. Uplinger , Candace J. F. Freedenberg
发明人： Robert G. Baker , Kevin Kettler , Gustavo A. Suarez , Kenneth A. Uplinger , Candace J. F. Freedenberg
IPC分类号： G03B15/00 , G02B3/00 , G02B6/04 , G02B6/06 , G02B13/04 , G02B13/06 , G02B13/16 , G03B19/00 , G06T1/00 , H04N5/225 , H04N5/232 , H04N5/262 , H04N7/14 , H04N7/15 , H04N7/18
CPC分类号： H04N7/142 , G02B13/06 , G02B3/0087 , G02B6/04 , G02B6/06 , H04N5/2628 , H04N7/15
摘要： A system for electronic imaging of a hemispheric field of view includes a camera for receiving optical images of the field of view and for producing output data corresponding to the optical images. The camera includes an optical assembly for producing images throughout a hemispheric field of view for optical conveyance to an imaging device or photographic film. The optical system assembly has lens components that selectively emphasize the peripheral content of the hemispheric field of view. An electronic imaging device within the camera or a film-to-digital date conversion system provides digitized output signals to input image memory or electronic storage devices. A transform processor selectively accesses and processes the digitized output signals from the input image memory according to user-defined criteria and stores the signals in output image memory. The signals in the output image memory can then be displayed according to the user-defined criteria.
摘要翻译：用于半球视场的电子成像系统包括：摄像机，用于接收视野的光学图像，并产生对应于光学图像的输出数据。相机包括用于在整个半球视野内产生图像以用于光学传输到成像装置或摄影胶片的光学组件。光学系统组件具有选择性地强调半球视野的周边内容的透镜部件。相机内的电子成像设备或电影数字日期转换系统向输入图像存储器或电子存储设备提供数字化的输出信号。变换处理器根据用户定义的标准选择性地访问和处理来自输入图像存储器的数字化输出信号，并将该信号存储在输出图像存储器中。然后可以根据用户定义的标准显示输出图像存储器中的信号。

5. 发明授权

US5363497A System for removing section of memory from first system and allocating to second system in a manner indiscernable to both operating systems 失效
标题翻译：用于从第一系统中去除存储器部分并以对两个操作系统不可理解的方式分配给第二系统的系统
公开(公告)号：US5363497A
公开(公告)日：1994-11-08
申请号：US128760
申请日：1993-09-30
申请人： Ernest D. Baker , John M. Dinwiddie, Jr. , Lonnie E. Grice , John M. Loffredo , Kenneth R. Sanderson , Gustavo A. Suarez
发明人： Ernest D. Baker , John M. Dinwiddie, Jr. , Lonnie E. Grice , John M. Loffredo , Kenneth R. Sanderson , Gustavo A. Suarez
IPC分类号： G06F9/46 , G06F9/50 , G06F11/16 , G06F12/02 , G06F13/18 , G06F15/16 , G06F15/167 , G06F15/177
CPC分类号： G06F9/5016 , G06F11/1641 , G06F11/1658 , G06F11/1679 , G06F15/161
摘要： The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques, The S/370 is limit checked prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.
摘要翻译：两个虚拟操作系统（例如，S / 370VM，VSE或IX370和S / 88OS）的功能被合并到一个物理系统中。 S / 88处理器的合作伙伴对运行S / 88操作系统，并处理系统的容错和单系统映像方面。 S / 370处理器的一个或多个伙伴对直接和通过S / 88总线耦合到对应的S / 88处理器。每个S / 370处理器从S / 88主存储器分配从1到16兆字节的连续存储。每个S / 370虚拟操作系统认为其存储器分配从地址0开始，并且通过正常的S / 370动态存储器分配和寻呼技术管理其存储器.S / 370是限制检查，防止S / 370访问S / 88 内存空间。 S / 88操作系统是所有系统硬件和I / O设备的主控。 S / 88处理器直接响应于S / 88应用程序来访问S / 370地址空间，使得S / 88可以将I / O数据移动到S / 370 I / O缓冲器中并且分别处理S / 370 操作系统在单个系统环境中，而不会显着重写任一操作系统。操作系统都不知道其他操作系统和其他处理器对。

6. 发明授权

US5325517A Fault tolerant data processing system 失效
标题翻译：容错数据处理系统
公开(公告)号：US5325517A
公开(公告)日：1994-06-28
申请号：US353116
申请日：1989-05-17
申请人： Ernest D. Baker , John M. Dinwiddie, Jr. , Lonnie E. Grice , James M. Joyce , John M. Loffredo , Kenneth R. Sanderson , Gustavo A. Suarez
发明人： Ernest D. Baker , John M. Dinwiddie, Jr. , Lonnie E. Grice , James M. Joyce , John M. Loffredo , Kenneth R. Sanderson , Gustavo A. Suarez
IPC分类号： G06F11/18 , G06F11/00 , G06F11/10 , G06F11/16 , G06F11/20 , G06F15/16 , G06F15/173 , G06F15/177
CPC分类号： G06F11/1641 , G06F11/10 , G06F11/1008 , G06F11/1482 , G06F11/16 , G06F11/20
摘要： The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.
摘要翻译：两个虚拟操作系统（例如，S / 370VM，VSE或IX370和S / 88OS）的功能被合并到一个物理系统中。 S / 88处理器的合作伙伴对运行S / 88操作系统，并处理系统的容错和单系统映像方面。 S / 370处理器的一个或多个伙伴对直接和通过S / 88总线耦合到对应的S / 88处理器。每个S / 370处理器从S / 88主存储器分配从1到16兆字节的连续存储。每个S / 370虚拟操作系统认为其存储器分配从地址0开始，并且通过正常的S / 370动态存储器分配和寻呼技术管理其存储器。 S / 370被限制检查以防止S / 370访问S / 88存储器空间。 S / 88操作系统是所有系统硬件和I / O设备的主控。 S / 88处理器直接响应S / 88应用程序来访问S / 370地址空间，以便S / 88可以将I / O数据移动到S / 370 I / O缓冲器中并处理S / 370 I / O操作。 S / 88和S / 370对等体处理器对在单个系统环境中执行其各自的操作系统，而不会显着地重写任一操作系统。操作系统都不知道其他操作系统和其他处理器对。

7. 发明授权

US5230041A Bus interface circuit for a multimedia system 失效
标题翻译：多媒体系统的总线接口电路
公开(公告)号：US5230041A
公开(公告)日：1993-07-20
申请号：US626791
申请日：1990-12-11
申请人： John M. Dinwiddie, Jr. , Bobby J. Freeman , Gustavo A. Suarez , Bruce J. Wilkie
发明人： John M. Dinwiddie, Jr. , Bobby J. Freeman , Gustavo A. Suarez , Bruce J. Wilkie
IPC分类号： G06F3/048 , G06F3/14 , G09G1/16 , G09G5/00
CPC分类号： G09G5/00 , G06F3/14 , G09G1/167
摘要： An information handling apparatus for transferring and composing image signals for display including a bus interface circuit adapted to allow selective access to a bus of an independent image signal generated by an independent image source. The selective access enables composition of the independent image signal in response to control information; the composition enables real time display of a composed image signal.

8. 发明授权

US5434590A Multimedia system 失效
标题翻译：多媒体系统
公开(公告)号：US5434590A
公开(公告)日：1995-07-18
申请号：US136724
申请日：1993-10-14
申请人： John M. Dinwiddie, Jr. , Bobby J. Freeman , Gustavo A. Suarez , Bruce J. Wilkie
发明人： John M. Dinwiddie, Jr. , Bobby J. Freeman , Gustavo A. Suarez , Bruce J. Wilkie
IPC分类号： G06F3/14 , G06T1/00 , G06T3/00 , G06T11/80 , G09G1/16 , G09G5/00 , G09G5/14 , H04H60/04 , H04N5/262
CPC分类号： H04N5/262 , G06F3/14 , G09G1/16 , G09G5/00 , H04N21/4143 , G09G1/167
摘要： An information handling apparatus for transferring and composing image signals including a plurality of media sources configured to provide a corresponding plurality of image signals, a media bus connected to the media sources, and a media control module coupled to the media bus. The media bus allows selective access for the plurality of image signals. The selective access enables composition of the independent image signals in response to control information. The media control module receives a composed image signal from the media bus and provides the composed image signal to a display device.
摘要翻译：一种用于传送和组合图像信号的信息处理装置，包括被配置为提供对应的多个图像信号的多个媒体源，连接到媒体源的媒体总线以及耦合到媒体总线的媒体控制模块。媒体总线允许选择性地访问多个图像信号。选择性访问可以响应于控制信息构成独立图像信号。媒体控制模块从媒体总线接收合成的图像信号，并将合成的图像信号提供给显示装置。

9. 发明授权

US5144692A System for controlling access by first system to portion of main memory dedicated exclusively to second system to facilitate input/output processing via first system 失效
标题翻译：用于控制第一系统访问主系统的系统专用于第二系统以便通过第一系统来辅助输入/输出处理
公开(公告)号：US5144692A
公开(公告)日：1992-09-01
申请号：US353113
申请日：1989-05-17
申请人： Ernest D. Baker , John M. Dinwiddie, Jr. , Lonnie E. Grice , John M. Loffredo , Kenneth R. Sanderson , Gustavo A. Suarez
发明人： Ernest D. Baker , John M. Dinwiddie, Jr. , Lonnie E. Grice , John M. Loffredo , Kenneth R. Sanderson , Gustavo A. Suarez
IPC分类号： G06F9/46 , G06F9/50 , G06F11/16 , G06F12/02 , G06F13/18 , G06F15/16 , G06F15/167 , G06F15/177
CPC分类号： G06F9/5016 , G06F11/1641 , G06F11/1658 , G06F11/1679 , G06F15/161
摘要： The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

10. 发明授权

US5113522A Data processing system with system resource management for itself and for an associated alien processor 失效
标题翻译：具有系统资源管理的数据处理系统及其相关的二进制处理器
公开(公告)号：US5113522A
公开(公告)日：1992-05-12
申请号：US353112
申请日：1989-05-17
申请人： John M. Dinwiddie, Jr. , Bobby J. Freeman , Lonnie E. Grice , John M. Loffredo , Kenneth R. Sanderson , Gustavo A. Suarez
发明人： John M. Dinwiddie, Jr. , Bobby J. Freeman , Lonnie E. Grice , John M. Loffredo , Kenneth R. Sanderson , Gustavo A. Suarez
IPC分类号： G06F15/16 , G06F9/46 , G06F11/16 , G06F15/177 , H04L29/00
CPC分类号： G06F11/1658 , G06F11/1641 , G06F11/1679 , G06F15/177 , H04L29/00 , G06F11/1608
摘要： The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contigous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

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