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1. 发明授权

US07704850B2 Semiconductor device for measuring an overlay error, method for measuring an overlay error, lithographic apparatus and device manufacturing method 有权
标题翻译：用于测量覆盖误差的半导体器件，测量覆盖误差的方法，光刻设备和器件制造方法
公开(公告)号：US07704850B2
公开(公告)日：2010-04-27
申请号：US11517571
申请日：2006-09-08
申请人： Mircea Dusa , Axel Nackaerts , Gustaaf Verhaegen
发明人： Mircea Dusa , Axel Nackaerts , Gustaaf Verhaegen
IPC分类号： H01L27/088
CPC分类号： G03F7/70658 , G03F7/70633 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device for determining an overlay error on a semiconductor substrate includes a first and a second transistor. Each transistor includes two diffusion regions associated with a gate, the diffusion regions of each transistor being arranged in a first direction. The second transistor is arranged adjacent to the first transistor in a second direction perpendicular to the first direction. The first and second gate each have a non-uniform shape, and the second gate is oriented with respect to an orientation of the first gate in such a way that an effect of an overlay error on a device parameter of the second transistor has an opposite sign in comparison to an effect of the overlay error on a corresponding device parameter of the first transistor.
摘要翻译：用于确定半导体衬底上的重叠误差的半导体器件包括第一和第二晶体管。每个晶体管包括与栅极相关联的两个扩散区域，每个晶体管的扩散区域沿第一方向布置。第二晶体管在垂直于第一方向的第二方向上被布置为与第一晶体管相邻。第一和第二栅极各自具有不均匀的形状，并且第二栅极相对于第一栅极的取向定向成使得第二晶体管的器件参数上的覆盖误差的影响具有相反的作用与覆盖误差对第一晶体管的相应器件参数的影响相比较。

2. 发明申请

US20110084313A1 Methods for Manufacturing Dense Integrated Circuits 审中-公开
标题翻译：制造密集集成电路的方法
公开(公告)号：US20110084313A1
公开(公告)日：2011-04-14
申请号：US12969441
申请日：2010-12-15
申请人： Liesbeth Witters , Axel Nackaerts , Gustaaf Verhaegen
发明人： Liesbeth Witters , Axel Nackaerts , Gustaaf Verhaegen
IPC分类号： H01L27/092 , H01L27/088
CPC分类号： H01L29/785 , H01L21/0337 , H01L21/3086 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L29/66795
摘要： One inventive aspect relates to a method for forming integrated circuits and circuits obtained therewith. The method of forming a circuit pattern in a device layer of a semiconductor substrate comprises decomposing the circuit pattern in two constituent orthogonal subpatterns. The method further comprises transferring the pattern of a first subpattern to a hard mask layer overlying the device layer. The method further comprises transferring the pattern of the other subpattern to a photosensitive layer overlying the patterned hard mask layer. The method further comprises patterning the device layer using the patterned hard mask layer and the patterned photosensitive layer as a mask. The method further comprises removing the patterned hard mask layer and the patterned photosensitive layer. Furthermore memory or logic circuits obtained using the above technique are described.
摘要翻译：本发明的一个方面涉及一种用于形成集成电路和由此获得的电路的方法。在半导体衬底的器件层中形成电路图形的方法包括在两个构成的正交子模式中分解电路图案。该方法还包括将第一子模式的图案转移到覆盖该器件层的硬掩模层。该方法还包括将另一子图案的图案转印到覆盖图案化的硬掩模层的感光层上。该方法还包括使用图案化的硬掩模层和图案化感光层作为掩模来图案化器件层。该方法还包括去除图案化的硬掩模层和图案化感光层。此外，描述使用上述技术获得的存储器或逻辑电路。

3. 发明申请

US20080061291A1 Semiconductor device for measuring an overlay error, method for measuring an overlay error, lithographic apparatus and device manufacturing method 有权
标题翻译：用于测量覆盖误差的半导体器件，测量覆盖误差的方法，光刻设备和器件制造方法
公开(公告)号：US20080061291A1
公开(公告)日：2008-03-13
申请号：US11517571
申请日：2006-09-08
申请人： Mircea Dusa , Axel Nackaerts , Gustaaf Verhaegen
发明人： Mircea Dusa , Axel Nackaerts , Gustaaf Verhaegen
IPC分类号： H01L23/58
CPC分类号： G03F7/70658 , G03F7/70633 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device for determining an overlay error on a semiconductor substrate includes a first and a second transistor. Each transistor includes two diffusion regions associated with a gate, the diffusion regions of each transistor being arranged in a first direction. The second transistor is arranged adjacent to the first transistor in a second direction perpendicular to the first direction. The first and second gate each have a non-uniform shape, and the second gate is oriented with respect to an orientation of the first gate in such a way that an effect of an overlay error on a device parameter of the second transistor has an opposite sign in comparison to an effect of the overlay error on a corresponding device parameter of the first transistor.
摘要翻译：用于确定半导体衬底上的重叠误差的半导体器件包括第一和第二晶体管。每个晶体管包括与栅极相关联的两个扩散区域，每个晶体管的扩散区域沿第一方向布置。第二晶体管在垂直于第一方向的第二方向上被布置为与第一晶体管相邻。第一和第二栅极各自具有不均匀的形状，并且第二栅极相对于第一栅极的取向定向成使得第二晶体管的器件参数上的覆盖误差的影响具有相反的作用与覆盖误差对第一晶体管的相应器件参数的影响相比较。

4. 发明申请

US20090217224A1 METHOD AND SYSTEM FOR MASK DESIGN FOR DOUBLE PATTERNING 审中-公开
标题翻译：用于双文件掩码设计的方法和系统
公开(公告)号：US20090217224A1
公开(公告)日：2009-08-27
申请号：US12390377
申请日：2009-02-20
申请人： Vincent Jean-Marie Pierre Paul Wiaux , Gustaaf Verhaegen
发明人： Vincent Jean-Marie Pierre Paul Wiaux , Gustaaf Verhaegen
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F1/44 , G03F1/70
摘要： A method and system for setting up multiple patterning lithographic processing of a pattern in a single layer is disclosed. The multiple patterning lithographic processing comprises a first and second patterning step. In one aspect, a method includes, for at least one process condition, obtaining values for a metric expressing a splitting correlated process quality as function of design parameters of a pattern and/or split parameters for the multiple patterning lithographic processing. The method also includes evaluating the values of the metric and selecting based thereon design and split parameters considering the process condition. The method may further include deriving design and/or split guidelines for splitting patterns to be processed using multiple patterning lithographic processing based on the evaluation.
摘要翻译：公开了一种用于在单层中设置图案的多重图案化光刻处理的方法和系统。多重图案化平版印刷处理包括第一和第二图案化步骤。在一个方面，一种方法包括对于至少一个处理条件，获得表示分割相关过程质量的度量的值作为用于多重图案化平版印刷处理的图案的设计参数和/或分割参数的函数。该方法还包括评估度量的值并且考虑到处理条件基于其设计和分割参数进行选择。该方法还可以包括基于评估，使用多个图案化平版印刷处理来导出用于分割待处理图案的设计和/或分割准则。

5. 发明申请

US20090112344A1 DESIGN OPTIMIZATION 有权
标题翻译：设计优化
公开(公告)号：US20090112344A1
公开(公告)日：2009-04-30
申请号：US12258261
申请日：2008-10-24
申请人： Axel Nackaerts , Gustaaf Verhaegen , Paul Marchal
发明人： Axel Nackaerts , Gustaaf Verhaegen , Paul Marchal
IPC分类号： G06F19/00
CPC分类号： G06F17/5068
摘要： A method for optimizing a design for a device is disclosed. Such an optimization is performed with respect to a predetermined metric, e.g. device speed, area, power consumption or yield. In one aspect, the method comprises obtaining a design for a device. The design comprises design components. The method also comprises determining from the design components at least one group of first design components that has a higher sensitivity to the predetermined metric than second design components. The first design components may be on the critical path in the design. The method further comprises tuning the first design components and the technology for manufacturing the first design components thus reducing the variability of the first design components and obtaining an optimized design with respect to the predetermined metric.
摘要翻译：公开了一种用于优化设备的设计的方法。相对于预定的度量，例如，设备速度，面积，功耗或产量。在一个方面，该方法包括获得设备的设计。该设计包括设计组件。该方法还包括从设计组件确定与第二设计组件相比具有比预定度量更高的灵敏度的至少一组第一设计组件。第一个设计组件可能在设计的关键路径上。该方法还包括调整第一设计组件和用于制造第一设计组件的技术，从而减少第一设计组件的可变性并获得关于预定度量的优化设计。

6. 发明申请

US20080149925A1 Semiconductor device for measuring an overlay error, method for measuring an overlay error, lithographic apparatus and device manufacturing method 有权
标题翻译：用于测量覆盖误差的半导体器件，测量覆盖误差的方法，光刻设备和器件制造方法
公开(公告)号：US20080149925A1
公开(公告)日：2008-06-26
申请号：US11826894
申请日：2007-07-19
申请人： Mircea Dusa , Axel Nackaerts , Gustaaf Verhaegen
发明人： Mircea Dusa , Axel Nackaerts , Gustaaf Verhaegen
IPC分类号： H01L23/58 , H01L27/088
CPC分类号： G03F7/70658 , G03F7/70633 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device for determining an overlay error on a semiconductor substrate includes a first and a second transistor. Each transistor includes two diffusion regions associated with a gate, the diffusion regions of each transistor being arranged in a first direction. The second transistor is arranged adjacent to the first transistor in a second direction perpendicular to the first direction. The first and second gate each have a non-uniform shape, and the second gate is oriented with respect to an orientation of the first gate in such a way that an effect of an overlay error on a device parameter of the second transistor has an opposite sign in comparison to an effect of the overlay error on the device parameter of the first transistor.
摘要翻译：用于确定半导体衬底上的重叠误差的半导体器件包括第一和第二晶体管。每个晶体管包括与栅极相关联的两个扩散区域，每个晶体管的扩散区域沿第一方向布置。第二晶体管在垂直于第一方向的第二方向上被布置为与第一晶体管相邻。第一和第二栅极各自具有不均匀的形状，并且第二栅极相对于第一栅极的取向定向成使得第二晶体管的器件参数上的覆盖误差的影响具有相反的作用与覆盖错误对第一晶体管的器件参数的影响进行比较。

7. 发明申请

US20070172770A1 Methods for manufacturing dense integrated circuits 审中-公开
标题翻译：密集集成电路制造方法
公开(公告)号：US20070172770A1
公开(公告)日：2007-07-26
申请号：US11645232
申请日：2006-12-22
申请人： Liesbeth Witters , Axel Nackaerts , Gustaaf Verhaegen
发明人： Liesbeth Witters , Axel Nackaerts , Gustaaf Verhaegen
IPC分类号： G03F7/20
CPC分类号： H01L29/785 , H01L21/0337 , H01L21/3086 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L29/66795
摘要： One inventive aspect relates to a method for forming integrated circuits and circuits obtained therewith. The method of forming a circuit pattern in a device layer of a semiconductor substrate comprises decomposing the circuit pattern in two constituent orthogonal subpatterns. The method further comprises transferring the pattern of a first subpattern to a hard mask layer overlying the device layer. The method further comprises transferring the pattern of the other subpattern to a photosensitive layer overlying the patterned hard mask layer. The method further comprises patterning the device layer using the patterned hard mask layer and the patterned photosensitive layer as a mask. The method further comprises removing the patterned hard mask layer and the patterned photosensitive layer. Furthermore memory or logic circuits obtained using the above technique are described.
摘要翻译：本发明的一个方面涉及一种用于形成集成电路和由此获得的电路的方法。在半导体衬底的器件层中形成电路图形的方法包括在两个构成的正交子模式中分解电路图案。该方法还包括将第一子模式的图案转移到覆盖该器件层的硬掩模层。该方法还包括将另一子图案的图案转印到覆盖图案化的硬掩模层的感光层上。该方法还包括使用图案化的硬掩模层和图案化感光层作为掩模来图案化器件层。该方法还包括去除图案化的硬掩模层和图案化感光层。此外，描述使用上述技术获得的存储器或逻辑电路。

8. 发明授权

US08136078B2 Optimization 有权
标题翻译：优化
公开(公告)号：US08136078B2
公开(公告)日：2012-03-13
申请号：US12258261
申请日：2008-10-24
申请人： Axel Nackaerts , Gustaaf Verhaegen , Paul Marchal
发明人： Axel Nackaerts , Gustaaf Verhaegen , Paul Marchal
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for optimizing a design for a device is disclosed. Such an optimization is performed with respect to a predetermined metric, e.g. device speed, area, power consumption or yield. In one aspect, the method comprises obtaining a design for a device. The design comprises design components. The method also comprises determining from the design components at least one group of first design components that has a higher sensitivity to the predetermined metric than second design components. The first design components may be on the critical path in the design. The method further comprises tuning the first design components and the technology for manufacturing the first design components thus reducing the variability of the first design components and obtaining an optimized design with respect to the predetermined metric.
摘要翻译：公开了一种用于优化设备的设计的方法。相对于预定的度量，例如，设备速度，面积，功耗或产量。在一个方面，该方法包括获得设备的设计。该设计包括设计组件。该方法还包括从设计组件确定与第二设计组件相比具有比预定度量更高的灵敏度的至少一组第一设计组件。第一个设计组件可能在设计的关键路径上。该方法还包括调整第一设计组件和用于制造第一设计组件的技术，从而减少第一设计组件的可变性并获得关于预定度量的优化设计。

9. 发明授权

US07786477B2 Semiconductor device for measuring an overlay error, method for measuring an overlay error, lithographic apparatus and device manufacturing method 有权
标题翻译：用于测量覆盖误差的半导体器件，测量覆盖误差的方法，光刻设备和器件制造方法
公开(公告)号：US07786477B2
公开(公告)日：2010-08-31
申请号：US11826894
申请日：2007-07-19
申请人： Mircea Dusa , Axel Nackaerts , Gustaaf Verhaegen
发明人： Mircea Dusa , Axel Nackaerts , Gustaaf Verhaegen
IPC分类号： H01L23/58
CPC分类号： G03F7/70658 , G03F7/70633 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device for determining an overlay error on a semiconductor substrate includes a first and a second transistor. Each transistor includes two diffusion regions associated with a gate, the diffusion regions of each transistor being arranged in a first direction. The second transistor is arranged adjacent to the first transistor in a second direction perpendicular to the first direction. The first and second gate each have a non-uniform shape, and the second gate is oriented with respect to an orientation of the first gate in such a way that an effect of an overlay error on a device parameter of the second transistor has an opposite sign in comparison to an effect of the overlay error on the device parameter of the first transistor.
摘要翻译：用于确定半导体衬底上的重叠误差的半导体器件包括第一和第二晶体管。每个晶体管包括与栅极相关联的两个扩散区域，每个晶体管的扩散区域沿第一方向布置。第二晶体管在垂直于第一方向的第二方向上被布置为与第一晶体管相邻。第一和第二栅极各自具有不均匀的形状，并且第二栅极相对于第一栅极的取向定向成使得第二晶体管的器件参数上的覆盖误差的影响具有相反的作用与覆盖错误对第一晶体管的器件参数的影响进行比较。

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